Data Sheet

November 2001

LCK4950
Low-Voltage PLL Clock Driver

Features

Fully integrated phase-locked loop (PLL)

Oscillator or crystal reference input

Output frequency up to 180 MHz

Outputs disable in high impedance

Compatible with PowerPC

, Intel

, and high-

performance RISC microprocessors

TQFP packaging

Output frequency configurable

±35 ps typical cycle-to-cycle jitter

Pin compatible with the Motorola

MPC950 clock

driver

Description

The LCK4950 is a PLL-based clock driver device
intended for high-performance clock tree designs.
The LCK4950 is 3.3 V compatible with output
frequencies of up to 180 MHz and output skews of
200 ps. The LCK4950 can accommodate the most
demanding tree designs by employing a fully
differential PLL design. This minimizes cycle-to-cycle
jitter, which is critical when the device is acting as the
reference clock for PLLs in today's microprocessors
and ASICs. The device has nine low-skew
configurable outputs for support of the clocking
needs of the various high-performance
microprocessors.

To provide input reference clock flexibility, two
selectable division ratios are available on the
LCK4950. The internal V

runs at either 2x or 4x

the high-speed output. The FBSEL pin is used to
select between a divide by 8 or a divide by 16 of the
V

frequency to be compared with the input

reference. These selections allow the input reference
to be either one-half, one-fourth, or one-eighth of the
high-speed output.

The LCK4950 is capable of scan clock distribution or
system diagnostics due to an external test clock
input. The REF_SEL pin allows the selection
between a crystal input to an on-chip oscillator for the
reference or selection of a TTL level oscillator input
directly. Only a parallel resonant crystal is required
for the onboard crystal oscillator external
components.

The LCK4950 is fully 3.3 V compatible and requires
no external loop filter components. All inputs accept
LVCMOS or LVTTL compatible levels while the
outputs provide LVCMOS levels with the capability to
drive terminated 50

transmission lines. The

LCK4950 can drive two traces, giving the device an
effective fan out of 1:18 for series-terminated 50

lines. For optimum performance and board density,
the device is packaged in a 7 mm x 7 mm 32-lead
TQFP package.

Agere Systems Inc.

Data Sheet
November 2001

Low-Voltage PLL Clock Driver

LCK4950

Pin Information

5-9699 (F)

Figure 2. Pin Diagram

Functional Description

Table 1. Function Tables

Ref_Sel

Function

TCLK

XTAL_OSC

PLL_En

Function

PLL Enabled

PLL Bypass

FBsel

Function

MR/OE

Function

Outputs Disabled

Outputs Enabled

fseln

Function

Qa =

4; Qb:d =

Qa =

2; Qb:d =

LCK4950

TCLK

PLL_En

Ref_Sel

Qd2

Qd3

Qd4

MR/OE

xtal2

l
d

l
c

l
b

l
a

DDA

Agere Systems Inc.

Data Sheet

November 2001

Low-Voltage PLL Clock Driver

LCK4950

Functional Description

(continued)

Table 2. Function Table

Note: x = fVCO/4; 200 MHz < fVCO < 480 MHz.

Table 3. PLL Input Reference Characteristics

* Maximum and minimum input reference is limited by the V

lock range and the feedback divider for the TCLK or xtal1 inputs.

See the Applications section for more crystal information.

Inputs

Outputs

Totals

fsela

fselb

fselc

fseld

Qa(1)

Qb(1)

Qc(2)

Qd(5)

Total 2x

Total x

Total x/2

x/2

Characteristic

Symbol

Min

Max

Unit

TCLK Input Rise/Falls

, t

3.0

Reference Input Frequency

ref

--*

MHz

Crystal Oscillator Frequency

Xtal

12.5

MHz

Reference Input Duty Cycle

refdc

Agere Systems Inc.

Data Sheet
November 2001

Low-Voltage PLL Clock Driver

LCK4950

Applications

Programming the LCK4950S

Several frequency relationships are configurable by the LCK4950. Frequency ratios of 1:1, 2:1, 4:1, and 4:2:1 are
possible from configuring the output dividers for the four output groups. To ensure that the output duty cycle is
always 50%, the LCK4950 uses even dividers. Table 4 illustrates output configurations of the LCK4950, describing
the outputs using the V

frequency as a reference. For example, setting the Qa outputs to V

/2, the Qb and Qc

to V

/4, and the Qd to V

/8 would provide the output frequency relationship of 4:2:1.

Table 4. Programmable Output Frequency Relationships

The division settings establish the output relationship, but one must still ensure that the V

will be stable given the

frequency of the outputs desired. The feedback frequency should be used to situate the V

into a frequency

range in which the PLL will be stable. The design of the PLL is such that for output frequencies between 25 MHz
and 180 MHz, the LCK4950 can generally be configured into a stable region.

Inputs

Outputs

FSELA

FSELB

FSELC

FSELD

Agere Systems Inc.

Data Sheet

November 2001

Low-Voltage PLL Clock Driver

LCK4950

Applications

(continued)

Table 5. Input Reference vs. Output Frequency Relationships

The relationship between the input reference and the output frequency is very flexible. Table 5 shows the
multiplication factors between the inputs and outputs for the LCK4950. Figure 3 through Figure 6 illustrate several
programming possibilities.

Note: The variations of the configurations shown are not complete, but do represent potential applications.

Config

fsela

fselb

fselc

fseld

FB_Sel = 1

FB_Sel = 0

Agere Systems Inc.

Data Sheet
November 2001

Low-Voltage PLL Clock Driver

LCK4950

Applications

(continued)

5-9700 (F)

Figure 3. Dual-Frequency Configuration

5-9701 (F)

Figure 4. Dual-Frequency Configuration

66.66 MHz

33.33 MHz

66.66 MHz

fsela

fselb

fselc

fseld

FBsel

INPUT REF

16.66 MHz

33.33 MHz

66.66 MHz

fsela

fselb

fselc

fseld

FBsel

INPUT REF

33.33 MHz

5-9702 (F)

Figure 5. Dual-Frequency Configuration

5-9703 (F)

Figure 6. Triple-Frequency Configuration

33.33 MHz

66.66 MHz

fsela

fselb

fselc

fseld

FBsel

INPUT REF

16.66 MHz

40 MHz

80 MHz

160 MHz

fsela

fselb

fselc

fseld

FBsel

INPUT REF

20 MHz

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.

Table 6. Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Unit

Supply Voltage

, V

DDA

0.3

4.6

Input Voltage

0.3

+ 0.3

Input Current

±20

Storage Temperature Range

Stor

125

°C

Agere Systems Inc.

Data Sheet

November 2001

Low-Voltage PLL Clock Driver

LCK4950

Electrical Characteristics

Table 7. dc Characteristics

= 0 °C to 70 °C, V

= 3.3 V ± 5%.

Table 8. ac Characteristics

= 0 °C to 70 °C, V

= 3.3 V ± 5%.

Characteristic

Symbol

Min

Typ

Max

Unit

Condition

Input High Voltage (LVCMOS inputs)

2.0

3.6

Input Low Voltage (LVCMOS inputs)

0.8

Output High Voltage

2.4

40 mA

1. The LCK4950 outputs can drive series or parallel-terminated 50

(or 50

to V

/2) transmission lines on the incident edge.

Output Low Voltage

0.5

= 40 mA

Input Current

±120

µA

Input Capacitance

Power Dissipation Capacitance

Per Output

Maximum Quiescent Supply Current

Non-PLL

DDQ

All V

Pins

Except V

DDA

2. Total power = (I

DDPLL

+ I

DDQ

) x V + (fQaCQa + fQbCQb + fQc0CQc0 + fQc1CQc1 + fQd0CQd0 + fQd1CQd1 + fQd2CQd2 + fQd3CQd3 +

fQd4CQd4) x V

; where V = V

DD, CQa

= load capacitance on Qa, CQb = load capacitance on Qb, etc.

Maximum PLL Supply Current

DDPLL

DDA

Pin Only

Characteristic

Symbol

Min

Typ

Max

Unit

Condition

Output Rise/Fall Time

, t

0.10

1.0

0.8 V to 2.0 V

Output Duty Cycle

48.5

52.5

Same Frequencies

Output-to-Output Skews

sk(0)

150

300

Different Frequencies:

fmax

< 150 MHz

fmax

> 150 MHz

--
--

200

400
400

ps
ps

--
--

PLL V

(feedback = V

/4)

Lock (feedback = V

/8)

Range (feedback = V

/16)

VCO

200
200
200

--
--
--

480
480
480

MHz
MHz
MHz

--
--
--

Maximum Output Frequency:

Qa(

Qa/Qb (

Qb (

max

--
--
--

180
120

MHz
MHz
MHz

--
--
--

Output Disable Time

PLZ,HZ

Output Enable Time

PZL

Cycle-to-Cycle Jitter (peak-to-peak)

jitter

±35

±50

1.See Applications section for more information.

Maximum PLL Clock Time

lock

Agere Systems Inc.

Data Sheet
November 2001

Low-Voltage PLL Clock Driver

LCK4950

Electrical Characteristics

(continued)

Jitter Performance of the LCK4950S

More focus is given to clock distribution design and management today because of the continuing increase of
today's digital system's clock rates. System-clock jitter and its effect on overall system timing budget is at the
center of this focus. The LCK4950 is designed to utilize a differential CMOS PLL and incorporate multiple power
and ground pins in the design to minimize clock jitter. The following text provides details on the jitter performance,
illustrates measurement limitations, and provides guidelines to minimize the jitter of the LCK4950.

The most commonly specified jitter parameter is cycle-to-cycle jitter. With today's high-performance measurement
equipment, there is no way to measure this parameter for jitter performance in the class demonstrated by the
LCK4950. As a result, different methods are used which approximate cycle-to-cycle jitter. The typical method of
measuring the jitter is to accumulate a large number of cycles, create a histogram of the edge placements, and
record peak-to-peak as well as standard deviations of the jitter. It is of great importance to measure the edge
immediately following the trigger edge. If this is not the case, the measurement inaccuracy will add significantly to
the measured jitter. The oscilloscope cannot collect adjacent pulses. It is safe to assume that collecting pulse
information in this mode will produce jitter values somewhat larger than if consecutive cycles were measured;
therefore, this measurement will represent an upper bound of cycle-to-cycle jitter. Most likely, this is a conservative
estimate of the cycle-to-cycle jitter.

There are two common sources of jitter for a PLL-based clock driver. The most common source of jitter is random
jitter. Less commonly known is the jitter produced by different frequency outputs switching synchronously. If all of
the outputs are switching at the same frequency, the PLL jitter is equal to the total jitter of the device. In the
LCK4950, where a number of the outputs can be switching synchronously but at different frequencies, a
multimodal jitter distribution can be seen on the highest frequency outputs. It is important to consider what is
happening on the other outputs because the output being monitored is affected by the activity on the other outputs.
From Figure 7, one can see that for each rising edge on the higher-frequency signal, the activity on the lower-
frequency signal is not consistent.

The placement of the edge that is being monitored is displaced in time due to the activity on the other outputs
altering the internal thresholds of the device. The relationship is periodic because the signals are synchronous.
The resulting jitter is a superposition of the PLL jitter on the displaced edges. The multimodal distribution will
appear to be a fat Gaussian distribution, or a truly multimodal distribution depending on the size of the PLL jitter
and displacement of the edges. When all the outputs are switching at the same frequency, there is no edge
displacement and the jitter is that of the PLL.

Agere Systems Inc.

Data Sheet
November 2001

Low-Voltage PLL Clock Driver

LCK4950

Electrical Characteristics

(continued)

5-9707 (F)

Figure 8. Power Supply Filter

PLL jitter can be measured for configurations where
the outputs are switching at different frequencies by
triggering the lowest-frequency output. PLL jitter is
dependent on internal V

frequency more so than

output configuration.

There are some general guidelines that will minimize
the output jitter of the device. First, always configure
the device so the V

runs as fast as possible. This is

the most important aspect in minimizing jitter of the
LCK4950. Second, maintain the reference frequency at
the highest possible frequency. These more frequent
phase detector updates help to reduce jitter. There is a
trade-off between higher reference frequencies and
higher V

frequency; always choose a higher V

frequency to reduce jitter. Third, and the most difficult
to follow, minimize the number of different frequencies
sourced from a single chip. The fixed edge
displacement associated with the switching noise, in
most cases, nearly doubles the effective jitter of a high-
speed output.

Power Supply Filtering

The LCK4950 exhibits some sensitivities that would not
be seen on a fully digital product because the LCK4950
is a mixed analog/digital product. Analog circuitry is
naturally sensitive to random noise, most noticeably
when the noise is in the power supply pins. The
LCK4950 provides a separate output buffer power
supply (V

) and phase-locked loop (V

DDA

) power

supply pins. This design isolates the high
switching noise digital outputs from the sensitive
internal analog phase-locked loop. In a controlled
setup (i.e., an evaluation board), this amount of
isolation will suffice. In a digital system, where it is
much more difficult to minimize noise on the power
supplies, an additional level of isolation may be
required. The easiest means of accomplishing this is
by applying a power supply filter on the V

DDA

pin for

the LCK4950.

Figure 8 illustrates a typical power supply filter scheme
for the LCK4950. The device is most greatly affected
by spectral content in the 1 kHz to 1 MHz range, and
therefore needs a filter to target this range. The most
important aspect of this final filter design is the dc
voltage drop between the V

supply and V

DDA

pin.

The I

DDPLL

current (current forced through the V

DDA

pin) is normally 45 mA (55 mA maximum), assuming
that a minimum of 3.0 V must be maintained on the
V

DDA

pin. Very little voltage drop can be tolerated when

a 3.3 V V

supply is used. The resistor shown in

Figure 10 must have a resistance of 5

--10

to meet

the voltage drop criteria. The RC filter shown provides
a broadband filter with about 100:1 attenuation for
noise, with a spectral content above 20 kHz. As the
noise frequency crosses the series resonant point of an
individual capacitor, its overall impedance begins to
look inductive and therefore increases with increasing
frequency. The parallel capacitor circuit shown in
Figure 11 guarantees that a low- impedance path to
ground exists for frequencies exceeding the bandwidth
of the PLL. It is recommended that the user start with
an 8

--10

resistor to avoid potential V

drop

problems and only use higher-value resistors when a
higher level of attenuation is needed.

The LCK4950 has several design features to minimize
the susceptibility to power supply noise (isolated power
and grounds and fully differential PLL). Still, there may
be applications in which overall performance is being
degraded due to system power supply noise. The
power supply filter schemes discussed in this section
should be adequate to eliminate power supply noise-
related problems in most designs.

0.01

--10

PLL_V

LCK4950

0.01

3.3 V

Agere Systems Inc.

Data Sheet

November 2001

Low-Voltage PLL Clock Driver

LCK4950

Electrical Characteristics

(continued)

Using the On-Chip Crystal Oscillator

The LCK4950 features an on-chip crystal oscillator buffer to allow for seed clock generation as well as final
distribution. The only external component required is the crystal since the on-chip oscillator buffer is completely
self-contained. The user is advised to mount the crystal as close to the LCK4950 as possible to avoid board-level
parasitics since the oscillator is, to a degree, sensitive to loading at the inputs. To facilitate collocation, surface-
mount crystals are recommended, but not required.

The oscillator circuit is a parallel resonant circuit with on-chip shunt capacitors. A parallel resonant crystal is simply
a crystal that has been characterized in its parallel resonant mode. Therefore, in the majority of cases, a parallel
specified crystal or a series resonant crystal can be used with the LCK4950 with just a minor frequency error.
Typically, a series crystal used in a parallel resonant mode will exhibit an oscillatory frequency a few hundred ppm
different than the specified value. For most processor implementations, a few hundred ppm translates into kHz
inaccuracies, a small enough level not to represent a major issue.

The LCK4950 is a clock driver that was designed to generate outputs with programmable frequency relationships.
As a result, the crystal input frequency is a function of the desired output frequency. To determine the crystal
required to produce the desired output frequency for an application that utilizes internal feedback, the PLL block
diagram (Figure 9) should be used. The P and the M values for the LCK4950 are also included in Figure 9. The M
values can be found in Table 1 on page 3.

Table 9. Crystal Specifications

Parameter

Value

Crystal Cut

Fundamental AT Cut

Resonance

Parallel Resonance

Frequency Tolerance

±75 ppm at 25 °C

Frequency/Temperature Stability

±150 ppm at 0

°C to 70 °C

Operating Range

°C to 70 °C

Shunt Capacitors

10 pF--40 pF

Equivalent Series Resistance (ESR)

to 80

Max

Correction Drive Level

100 µW

Aging

5 ppm/yr (first three years)

Agere Systems Inc.

Data Sheet
November 2001

Low-Voltage PLL Clock Driver

LCK4950

Electrical Characteristics

(continued)

5-9708 (F)

Figure 9. PLL Block Diagram

Note: For computations refer to the following equations:

m = 8 (FBsel = 1), 16(FBsel = 0), P = 1

For the LCK4950 clock driver, the following will provide an example of how to determine the crystal frequency
required for a given design.

Given:

Qa = 160 MHz
Qb = 80 MHz
Qc = 40 MHz
Qd = 40 MHz
FBSel = 0

(eq. 1)

From Figure 3:

fQd = V

/8 then N = 8 or fQa = V

/2 then N = 2

From Figure 9:

m = 16 and P = 1

PHASE

DETECTOR

LPF

ref

VCO

--------------

vco

ref

fQn

------------------------------

ref

fQn

------------------------------

ref

------------------------

20 MHz

ref

160

----------------------------

20 MHz

Agere Systems Inc.

Data Sheet

November 2001

Low-Voltage PLL Clock Driver

LCK4950

Electrical Characteristics

(continued)

Driving Transmission Lines

The LCK4950 clock driver was designed to drive high-speed signals in a terminated transmission line environment.
The output drivers were designed to exhibit the lowest impedance possible to provide the optimum flexibility to the
user. With an output impedance of less than 10

the drivers can drive either parallel-terminated or series-

terminated transmission lines.

Point-to-point distribution of signals is the method of choice in most high-performance clock networks. In a point-to-
point scheme, either series-terminated or parallel-terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a 50

resistance to V

/2. Only a single terminated line

can be driven by each output of the LCK4950 clock driver because this technique draws a fairly high level of dc
current. For the series driven case, however, there is no dc current draw and the outputs can drive multiple series-
terminated lines. Figure 10 illustrates an output driving a single series-terminated line.

5-9709 (F)

Figure 10. Single Transmission Line

The situation in Figure 11 should be used to better match the impedances when driving multiple lines. In this case,
the series-terminating resistors are reduced so when the parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.

5-9710 (F)

Figure 11. Optimized Dual Line Termination

OUTPUT

BUFFER

= 43

= 50

OutA

OUTPUT

BUFFER

= 36

= 50

= 36

= 50

PowerPC is a registered trademark of International Business Machines Corporation.
Intel is a registered trademark of Intel Corporation.
Motorola is a registerd trademark of Motorola, Inc.

November 2001
DS02-033HSI (Replaces DS01-118ANET)

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

For additional information, contact your Agere Systems Account Manager or the following:
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http://www.agere.com

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