Document Outline

• Table of Contents
• Figures
• Tables
• 1.0 Introduction
  • 1.1 Features
  • 1.2 Glossary of Terms
  • 1.3 Document Conventions
    • Figure 1 : Functional Block Diagram
• 2.0 Data and Configuration Input/Output
  • 2.1 Configuration Writes
    • Figure 2 : Configuration Cycle Followed by Block 1
    • Figure 3 : Configuration Header for Consecutive Blocks
    • Figure 4 : Fixed Configuration Mode
    • Figure 5 : Configuration Example for Gaps Between Configuration Writes
  • 2.2 Configuration Reads
  • 2.3 Configuration Cycle Format
  • 2.4 Decoder Status Output
  • 2.5 Decoder Status Output Format
  • 2.6 Encoder and Decoder - Synchronous I/O - Full Duplex
    • Figure 6 : Full Duplex Connection Diagram
    • Figure 7 : Synchronous Data/Configuration Communication Timing - Start of Block
    • Figure 8 : Synchronous Data/Configuration Communication Timing - End of Block
  • 2.7 Encoder and Decoder Synchronous - Half Duplex
    • Figure 9 : Half Duplex Connection Diagram
  • 2.8 Bus Mode - Half Duplex
    • Figure 10 : Half Duplex Connection Diagram
    • Figure 11 : Bus Interface Data/Configuration Communication Timing - Start of Block
  • 2.9 Decoder Bus Interface, Encoder Synchronous Interface - Full Duplex
    • Figure 12 : Full Duplex Connection Diagram
• 3.0 Encoder
  • Figure 13 : Encoder Block Diagram
  • 3.1 CRC Encoder
    • Figure 14 : CRC Encoder
    • Table 1 : Recommended CRC Polynomials
    • Figure 15 : 2D TPC Encoded Block with CRC
  • 3.2 Scrambler
    • Figure 16 : Scrambler
  • 3.3 TPC Encoder
    • 3.3.1 Encoder Code Shortening
      • Figure 17 : Structure of Shortened Code
    • 3.3.2 Helical Interleaver
      • Figure 18 : Input Block
      • Figure 19 : 2D Interleaving
      • Figure 20 : Encoded/Interleaved Data Output
    • 3.3.3 Internal Buffering
    • 3.3.4 Encoder Rapid Code Reconfiguration
      • Figure 21 : Encoder Rapid Code Reconfiguration with Helical Interleaving Disabled
      • Figure 22 : Encoder Rapid Code Reconfiguration with Helical Interleaving Enabled
    • 3.3.5 Encoder Latency
• 4.0 Decoder
  • 4.1 Channel Interface
    • 4.1.1 Channel Input Formatting
      • Figure 23 : C_DATA Interface
  • 4.2 TPC Decoder
    • 4.2.1 Helical Deinterleaver
    • 4.2.2 Code Configuration
    • 4.2.3 Decoder Code Shortening
    • 4.2.4 Corrections Count
    • 4.2.5 Descrambler
    • 4.2.6 CRC Checking
    • 4.2.7 Decoder Rapid Code Reconfiguration
      • Figure 24 : Decoder Rapid Code Reconfiguration
    • 4.2.8 Decoder Latency
      • Table 2 : Partial Code List and Decoder Datapath Latency
      • Table 3 : Partial Code List and Performance - Synchronous Interface
      • Table 4 : Partial Code List and Performance - Bus Interface
    • 4.2.9 Code Performance
• 5.0 Phase Lock Loop
• 6.0 General Output Signals
• 7.0 Register Descriptions
  • 7.1 Configuration Sequence
  • 7.2 Register List
    • Table 5 : Register Bits - Alphabetical
  • 7.3 User Data Formatting Registers
    • 7.3.1 CRC and Scrambler Configuration
  • 7.4 Code Configuration Registers
    • 7.4.1 TPC Constituent Code
    • 7.4.2 Block Size
    • 7.4.3 Buffer Configuration (Encoder Only)
    • 7.4.4 Shortening Configuration
      • Table 6 : Summary of Code Shortening Rules
    • 7.4.5 Feedback (Decoder Only)
    • 7.4.6 Iterations (Decoder Only)
  • 7.5 Channel Interface Registers
    • 7.5.1 Quantization (Decoder Only)
  • 7.6 Data Input/Output Configuration
    • 7.6.1 Transfer Word Size
  • 7.7 Control and Status
    • 7.7.1 Control
    • 7.7.2 Status and Correction Count (Decoder Only)
    • 7.7.3 Actual Iterations (Decoder Only)
  • 7.8 Miscellaneous
    • 7.8.1 Version
• 8.0 Signal Descriptions
  • 8.1 System Control and Miscellaneous
  • 8.2 Unencoded Data Interface
  • 8.3 Encoded Data Interface
  • 8.4 Channel Data Interface
  • 8.5 Decoded Data Interface
• 9.0 Pinout
  • Table 7 : Pinout - Pin Number Order
  • Figure 25 : Pinout
• 10.0 DC Electrical Specifications
  • 10.1 Operating Conditions
  • 10.2 Absolute Maximum Stress Ratings
  • 10.3 Test Conditions
    • Figure 26 : Signal Timing vs. Output Load
• 11.0 AC Electrical Specifications
  • 11.1 SYSCLK Clock Timing
    • Figure 27 : SYSCLK Clock Timing
    • Table 8 : SYSCLK Clock Timing with PLLBYPASS = 0
    • Table 9 : SYSCLK Clock Timing with PLLBYPASS = 1
  • 11.2 U_CLK, E_CLK, C_CLK, D_CLK Clock Timing
    • Figure 28 : Clock Timing
    • Table 10 : Clock Timing
  • 11.3 U_WR_N, E_RD_N, C_WR_N, D_RD_N Strobe Timing
    • Figure 29 : Strobe Timing
    • Table 11 : Strobe Timing with PLLBYPASS = 0
  • 11.4 Synchronous Data Interface
    • Figure 30 : Encoder Interface Data Input Timing
    • Table 12 : Encoder Interface Data Input Timing
    • Figure 31 : Decoder Interface Data Input Timing
    • Table 13 : Decoder Interface Data Input Timing
    • Figure 32 : Encoder Interface Data Output Timing Using Chip Select
    • Table 14 : Encoder Interface Data Output Timing Using Chip Select
    • Figure 33 : Encoder Interface Data Ouput Timing
    • Table 15 : Encoder Interface Data Output Timing
    • Figure 34 : Decoder Interface Data Output Timing Using Chip Select
    • Table 16 : Decoder Interface Data Output Timing Using Chip Select
    • Figure 35 : Decoder Interface Data Output Timing
    • Table 17 : Decoder Interface Data Output Timing
  • 11.5 Bus Interface
    • Figure 36 : Encoder Bus Interface Data Input Timing
    • Table 18 : Encoder Bus Interface Data Input Timing
    • Figure 37 : Decoder Bus Interface Data Input Timing
    • Table 19 : Decoder Bus Interface Data Input Timing
    • Figure 38 : Encoder Bus Interface Data Output Timing
    • Table 20 : Encoder Bus Interface Data Output Timing
    • Figure 39 : Decoder Bus Interface Data Output Timing
    • Table 21 : Decoder Bus Interface Data Output Timing
  • 11.6 Reset_n Timing
    • Figure 40 : RESET_N Timing
    • Table 22 : RESET_N Timing
• 12.0 Package Specifications
  • 12.1 Package Dimensions
    • Figure 41 : Package Dimensions - Top View
    • Figure 42 : Package Dimensions - Cross Section View
    • Table 23 : TQFP (Thin Quad Flat Pack) 7 x 7 mm Package Dimensions
• 13.0 Ordering Information
  • 13.1 Available Parts
  • 13.2 Part Numbering
• 14.0 Related Technical Publications
• Appendix A : Vad Recommendations