Document Outline

• Notes to Customers
• Table of Contents
  • 4.0 Register Descriptions 15
  • 5.0 Signal Descriptions 24
  • 6.0 Pinout 27
  • 7.0 DC Electrical Specifications 29
  • 8.0 AC Electrical Specifications 31
  • 9.0 Package Specifications 38
  • 10.0 Ordering Information 39
  • 11.0 About AHA 40
• Figures
• Tables
• 1.0 Introduction
  • 1.1 Conventions, Notations and Definitions
  • 1.2 Features
    • Figure 1 : Functional Block Diagram
  • 1.3 Functional Overview
    • Table 1 : Data Bus and FIFO Sizes Supported by StarLite
    • Table 2 : StarLite Connection to Host Microprocessors
• 2.0 System Configuration
  • 2.1 Microprocessor Interface
    • Table 3 : Microprocessor Port Configuration
    • Figure 2 : Microprocessor Port Write (PROCMODE[1:0]=�01�)
    • Figure 3 : Microprocessor Port Read (PROCMODE[1:0]=�01�)
    • Figure 4 : Microprocessor Port Write (PROCMODE[1:0]=�11�)
    • Figure 5 : Microprocessor Port Read (PROCMODE[1:0]=�11�)
• 3.0 Functional Description
  • 3.1 Data Ports
  • 3.2 DMA Mode
    • Table 4 : Internal Strobe Conditions for DMA Mode
    • Figure 6 : DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100
    • Figure 7 : DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100
    • Figure 8 : DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition ofDSC=100
    • Figure 9 : DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=100
    • Figure 10 : DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=100
    • Figure 11 : DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition ofDSC=100
  • 3.3 Pad Word Handling in BurstMode
  • 3.4 DMA Request Signals andStatus
    • 3.4.1 FIFO Thresholds
      • Figure 12 : FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO)
      • Figure 13 : Request vs. End-of-Record, Strobe Condition of DSC=010
    • 3.4.2 Request During an End-of- Record
    • 3.4.3 Request Status Bits
  • 3.5 Data Format
  • 3.6 Odd Byte Handling
    • 3.6.1 Compression Input and Pad Bytes
    • 3.6.2 Compression Output and PadBytes
    • 3.6.3 Decompression Input, Pad Bytes and Error Checking
    • 3.6.4 Decompression Output and PadBytes
  • 3.7 Video Interfaces
    • 3.7.1 Video Input
    • 3.7.2 Video Output
      • Figure 14 : Timing Diagram, Video Input
      • Figure 15 : Timing Diagram, Video Output
  • 3.8 Compression Engine
  • 3.9 Decompression Engine
  • 3.10 Interrupts
  • 3.11 Low Power Mode
  • 3.12 Test Mode
• 4.0 Register Descriptions
  • Table 5 : Internal Registers
  • 4.1 System Configuration 0, Address 0x00 - Read/Write
  • 4.2 System Configuration 1, Address 0x01 - Read/Write
  • 4.3 Input FIFO Thresholds, Address 0x02 - Read/Write
  • 4.4 Output FIFO Thresholds, Address 0x03 - Read/Write
  • 4.5 Compression Ports Status, Address 0x04 - Read Only
  • 4.6 Decompression Ports Status, Address 0x05 - Read Only
  • 4.7 Port Control, Address 0x06 - Read/Write
  • 4.8 Interrupt Status/Control, Address 0x07 - Read/Write
  • 4.9 Interrupt Mask, Address 0x09 - Read/Write
  • 4.10 Version, Address 0x0A - Read Only
  • 4.11 Decompression Record Length, Address 0x0C, 0x0D, 0x0E, 0x0F - Read/Write
  • 4.12 Record Length, Address 0x10, 0x11, 0x12, 0x13 - Read/Write
  • 4.13 Compression Control, Address 0x14 - Read/Write
  • 4.14 Compression Reserved, Address 0x15 - Read/Write
  • 4.15 Compression Configuration, Address 0x16, 0x17 - Read/Write
  • 4.16 Decompression Control, Address 0x18 - Read/Write
  • 4.17 Decompression Reserved, Address 0x1A - Read/Write
  • 4.18 Decompression Configuration, Address 0x1C, 0x1D - Read/Write
• 5.0 Signal Descriptions
  • 5.1 Microprocessor Interface
  • 5.2 Data Interface
  • 5.3 Video Interface
  • 5.4 System Control
• 6.0 Pinout
  • Figure 16 : Pinout
• 7.0 DC Electrical Specifications
  • 7.1 Operating Conditions
  • 7.2 Absolute Maximum Stress Ratings
    • Figure 17 : Power vs. Data Rate at 25 MHz Operation
• 8.0 AC Electrical Specifications
  • Figure 18 : Data Interface Timing
  • Table 6 : Data Port Timing Requirements
  • Figure 19 : Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=0
  • Figure 20 : Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=1
  • Figure 21 : Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0
  • Figure 22 : Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1
  • Table 7 : Request vs. EOR Timing
  • Figure 23 : Output Enable Timing
  • Table 8 : Output Enable Timing Requirements
  • Figure 24 : Video Input Port Timing
  • Table 9 : Video Input Port Timing Requirements
  • Figure 25 : Video Output Port Timing
  • Table 10 : Video Output Port Timing Requirements
  • Figure 26 : Microprocessor Interface Timing (PROCMODE[1]=0)
  • Figure 27 : Microprocessor Interface Timing (PROCMODE[1]=1)
  • Table 11 : Microprocessor Interface Timing Requirements
  • Figure 28 : Interrupt Timing
  • Table 12 : Interrupt Timing Requirements
  • Figure 29 : Clock Timing
  • Table 13 : Clock Timing Requirements
  • Figure 30 : Power On Reset Timing
  • Table 14 : Power On Reset Timing Requirements
• 9.0 Package Specifications
• 10.0 Ordering Information
  • 10.1 Available Parts
  • 10.2 Part Numbering
• 11.0 About AHA
• Appendix A : Additional Timing Diagrams for DMA Mode Transfers