comtech aha corporation
psG709E2-5_0804
A subsidiary of Comtech Telecommunications Corporation
i
Table of Contents
1.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.0 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1 ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 REED SOLOMON CODE PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3.0 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 INPUT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.2 OUTPUT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4.0 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.0 ABOUT AHA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
comtech aha corporation
psG709E2-5_0804
A subsidiary of Comtech Telecommunications Corporation
Page 1 of 2
1.0
INTRODUCTION
This G.709-2.5 core implements the RS(255,239)
code specified in Annex A of the ITU G.709
standard. It is designed to efficiently perform the
Reed Solomon encoding function specified by the
standard. The core requires no configuration, no
initialization, and no resynchronization procedure.
1.1
FEATURES
PERFORMANCE:
ITU G.709 Compatible Reed Solomon core
2.5 Gbits/sec operation in 0.13 micron CMOS
process with 332 MHz clock
One-edge, one clock fully synchronous design
Two clock latency
1K gates
Only initialization is a RESET
8 bit input and output data interfaces
DELIVERABLES:
ITU G.709 compatible RS Encoder core VHDL
Timing constraints (Design Compiler and Ambit
format)
Test bench and verification vectors (VHDL)
2.0
FUNCTIONAL DESCRIPTION
Figure 1:
BLOCK DIAGRAM
2.1
ENCODING
Uncoded block length is 239 Bytes with 16
check Bytes and a correction power of 8 Bytes per
block. Latency through the encoder is two clocks. A
global reset clears all of the flip-flops involved with
generating the parity check bytes.
Processing begins by applying the first data
byte on the DATA bus, asserting the START signal,
and then asserting the CLK signal. Every input byte
is then added with the REG15 output and the sum
input to all the Galois Field constant multipliers
(GFMx). The outputs of these multipliers are
summed with the previous stage value and clocked
into the next register stage. After processing all 239
bytes in this manner the 16 parity check bytes are
strobed out. This process of strobing out the parity
check bytes reinitializes the register stages in
preparation for processing the next block, thus not
requiring any additional RESET pulses.
2.2
REED SOLOMON CODE PARAMETERS
generator polynomial:
where
is a root of the binary primitive
polynomial x
8
+ x
4
+ x
3
+ x
2
+ 1 .
Parity bytes are represented by:
where R
j
(j = 0 to 15) is the parity byte
represented by an element out of GF(256) and R
15
corresponds to the byte 240 in the FEC sub-row and
R
0
to byte 255.
AHAG709-2.5 FEC Encoder
CLK
RESET
START
DATA[7:0]
OUT[7:0]
G z
( )
z
i
(
)
i
0
=
15
=
R z
( )
R
15
z
15
R
14
z
14
... R
1
z
1
R
0
+
+
+
=
comtech aha corporation
Page 2 of 2
A subsidiary of Comtech Telecommunications Corporation
psG709E2-5_0804
3.0
SIGNAL DESCRIPTIONS
3.1
INPUT INTERFACE
3.2
OUTPUT INTERFACE
4.0
TIMING DIAGRAMS
Figure 2:
FUNCTIONAL TIMING
5.0
ABOUT AHA
Comtech AHA Corporation (AHA) develops and markets superior integrated circuits, boards, and
intellectual property core technology for communications systems architects worldwide. AHA has been
setting the standard in Forward Error Correction and Lossless Data Compression technology for many years
and provides flexible, cost-effective solutions for today's growing bandwidth and reliability challenges.
Comtech AHA Corporation is a wholly owned subsidiary of Comtech Telecommuncations Corp.
(NASDAQ: CMTL). For more information, visit www.aha.com.
Signal
Type
Description
DATA[7:0]
I
Data Bus. Input data bus for information word.
START
I
Block start signal. This signal is asserted with the first byte
transfer of a block. Start signals should be at least 255 clocks
apart, but can be more than 255 clocks.
CLK
I
System Clock.
RESET
I
Global Reset. When active (high) RESET forces a reset on all of
the flip-flops involved in parity generation.
Signal
Type
Description
OUT[7:0]
O
Output data bus. Message Bytes are passed through onto this
bus followed by the 16 parity check bytes for each 239 Byte
block that is processed.
1
2
3
239
238
237
r15
r14
r13
r12
r1
r2
r0
1
2
1
2
3
4
5
239
1
2
3
4
CLK
RESET
START
DATA
OUT
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