ASAHI KASEI
[AK4683]
MS0427-E-01
2005/11
- 1 -
GENERAL DESCRIPTION
The AK4683 is a single chip CODEC that includes two channels of ADC and four channels of DAC. The ADC
outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit
architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit
architecture, and achieves wider dynamic range and lower outband noise. The also has digital audio receiver
(DIR) and transmitter (DIT) compatible with 192kHz, 24bits. The DIR can automatically detect a Non-PCM bit
stream such as Dolby Digital (AC-3)*.
The AK4683 has a dynamic range of 100dB for ADC, 106dB for DAC and is well suited for digital TV and
home theater system.
* Dolby Digital (AC-3) is a trademark of Dolby Laboratories.
FEATURES
ADC/DAC part
Asynchronous ADC/DAC Operation
6:1 Input Selector with Pre-amp
2ch 24bit ADC
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Single-Ended Input
- S/(N+D): 90dB
- Dynamic Range, S/N: 100dB
- Digital HPF for Offset Cancellation
- Channel Independent Digital Volume (+24/-103dB, 0.5dB/step)
- Soft Mute
- Overflow Flag
4ch 24bit DAC
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- Single-Ended Outputs
- S/(N+D): 90dB
- Dynamic Range, S/N: 106dB
- Channel Independent Digital Volume (+12/-115dB, 0.5dB/step)
- Soft Mute
- De-emphasis Filter (32kHz, 44.1kHz, 48kHz)
- Zero Detect Function
Stereo Headphone Amp with Volume
- 50mW at 16ohm
- Click-noise free at Power on/off
High Jitter Tolerance
Asynchronous Multi-Channel Audio CODEC with DIR/T
AK4683
ASAHI KASEI
[AK4683]
MS0427-E-01
2005/11
- 2 -
DIR/DIT Part
- AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible
- Low jitter Analog PLL
- PLL Lock Range : 32kHz to 192kHz
- Clock Source: PLL or X'tal
- 4-channel Receiver input
- 1-channel Transmission output (Through output or DIT)
- Auxiliary digital input
- De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz
- Detection Functions
Non-PCM Bit Stream Detection
DTS-CD Bit Stream Detection
Sampling Frequency Detection
(32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
Unlock & Parity Error Detection
Validity Flag Detection
- Up to 24bit Audio Data Format
- 40-bit Channel Status Buffer
- Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream
- Q-subcode Buffer for CD bit stream
TTL Level Digital I/F
External Master Clock Input:
- 256fs, 384fs, 512fs (fs=32kHz
48kHz)
- 128fs, 192fs, 256fs (fs=64kHz
96kHz)
- 128fs (fs=120kHz
192kHz)
Master Clock Output: 128fs/256fs/384fs/512fs
2 Audio Serial I/F (PORTA, PORTB)
- Master/Slave mode
- I/F format
PORTA: Left/Right(20/24 bit) justified, I
2
S, TDM
PORTB: Left/Right(20/24 bit) justified, I
2
S
4-wire Serial and I
2
C Bus
P I/F for mode setting
Operating Voltage: 4.5 to 5.5V
Power Supply for output buffer: 2.7 to 5.5V
64pin LQFP Package (0.5mm pitch)
ASAHI KASEI
[AK4683]
MS0427-E-01
2005/11
- 3 -
Block Diagram
ADC
Audio
I/F
ADC
LIN1
LIN2
LIN3
LIN4
LIN5
LIN6
HPF,
DVOL
DAC
DVOL
LPF
LOUT1
ROUT1
LOUT2
ROUT2
HPL
HPR
DAC
DVOL
LPF
DAC
DVOL
LPF
DAC
DVOL
LPF
DAC1
Audio
I/F
4:2
Input
Selector
Clock
Recovery
X'tal
Oscillator
P I/F
XTO
XTI
BICKB
LRCKB
TX
SDTOB
SDOUT
DAIF
Decoder
ADC
DIT
SDTIB
RIN1
RIN2
RIN3
RIN4
RIN5
RIN6
ROPIN
RISEL
I2C
CSN
CCLK
CDTI
CDTO
RX0
RX1
RX2
RX3
LISEL
LOPIN
SDTOB0/1 bit
DIT0/1 bit
DIT bit
MCLK2
SDTOA
OLRCKA
BICKA
ILRCKA
SDTIA1
SDTIA2
SDTIA3
MCKO
SDTOA0/1 bit
DIR
ADC
SDTIB
SDTIA1
Through
DIT
RMCLK
DAC10/11/12,
DAC20/21/22 bit
IPS0/1, OPS0/1 bit
LIN0/1/2, RIN0/1/2 bit
DIR
ADC
SDTIA1
off
DIR
ADC
SDTIB
off
DAC2
Audio
I/F
DIR
ADC
SDTIB
SDTIA1
SDTIA2
SDTIA3
HPF,
DVOL
DIR
ADC
SDTIB
SDTIA1
SDTIA2
SDTIA3
PORTB
PORTA
ASAHI KASEI
[AK4683]
MS0427-E-01
2005/11
- 4 -
Ordering Guide
AK4683EQ -20
+85C 64pin LQFP (0.5mm pitch)
AKD4683 Evaluation Board for AK4683
Pin Layout
PVDD
1
RX0
2
I2C
3
RX1
4
RX2
5
RX3
6
INT
7
VOUT
8
CDTO
9
LRCKB
10
BICKB
11
SDTOB
12
OLRCKA
13
ILRCKA
14
BICKA
15
SDTOA
16
64
R
63
PV
SS
62
RI
N6
61
LI
N6
60
RI
N5
59
LIN
5
58
RI
N4
57
LIN
4
56
RI
N3
55
LI
N3
54
RI
N2
53
LI
N2
52
RI
N1
51
LIN
1
50
A
V
DD1
49
17
MC
KO
18
TVD
D
19
DV
S
S
20
DV
DD
21
XTI
22
XT
O
23
T
X
24
MC
L
K
2
25
PD
N
26
CDT
I
27
CCL
K
28
CS
N
29
SDTI
A
1
30
SDTI
A
2
31
SDTI
A
3
32
SD
TI
B
RISEL
48
ROPIN
47
LOPIN
46
LISEL
45
AVSS2
44
AVDD2
43
VCOM
42
ROUT2
41
LOUT2
40
ROUT2
39
LOUT2
38
MUTET
37
HPL
36
HPR
35
HVSS
34
HVDD
33
AK4683EQ
Top View
A
V
SS1
Compatibility with AK4588
Functions AK4588
AK4683
DAC, ADC Asynchronous operation
NOT Available
Available
DAC ch#
8ch
4ch
HP-Amp - 2ch
ADC Input selector
-
6:1
ASAHI KASEI
[AK4683]
MS0427-E-01
2005/11
- 5 -
PIN/FUNCTION
No. Pin
Name I/O
Function
1 PVDD
- PLL Power supply Pin, 4.5V
5.5V
2
RX0
I
Receiver Channel 0 Pin (Internal biased pin. Internally biased at PVDD/2)
3 I2C
I
Control Mode Select Pin.
"L": 4-wire Serial, "H": I
2
C Bus
4
RX1
I
Receiver Channel 1 Pin
5
RX2
I
Receiver Channel 2 Pin
6
RX3
I
Receiver Channel 3 Pin
7 INT
O Interrupt
Pin
VOUT
O
V-bit Output Pin for Receiver Input
DZF O
Zero Input Detect Pin
When the input data of DAC follow total 8192 LRCK cycles with "0" input data, this
pin goes to "H". And when RSTN1 bit is "0", PWDA bit is "0", this pin goes to "H".
8
OVF O
Analog Input Overflow Detect Pin
This pin goes to "H" if the analog input of Lch or Rch overflows.
9
CDTO
O
Control Data Output Pin in Serial Mode and I2C pin = "L".
10
LRCKB
I/O Channel Clock B Pin
11
BICKB
I/O Audio Serial Data Clock B Pin
12
SDTOB
O
Audio Serial Data Output B Pin
13
OLRCKA
I/O Output Channel Clock A Pin
14
ILRCKA
I/O Input Channel Clock A Pin
15
BICKA
I/O Audio Serial Data Clock A Pin
16
SDTOA
O
Audio Serial Data Output A Pin
17
MCKO
O
Master Clock Output Pin
18 TVDD
- Output Buffer Power Supply Pin, 2.7V
5.5V
19
DVSS
-
Digital Ground Pin, 0V
20
DVDD -
Digital Power Supply Pin, 4.5V
5.5V
21
XTI
I
X'tal Input Pin
22
XTO
O
X'tal Output Pin
23 TX
O
Transmit Channel Output pin
When DIT bit = "0", RX0~3 Through.
When DIT bit = "1", Internal DIT Output.
24
MCLK2
I
Master Clock Input Pin
25 PDN
I
Power-Down Mode & Reset Pin
When "L", the AK4683 is powered-down, all registers are reset. And then all digital
output pins go "L". The AK4683 must be reset once upon power-up.
CDTI
I
Control Data Input Pin in Serial Mode and I2C pin = "L".
26
SDA
I/O
Control Data Pin in Serial Mode and I2C pin = "H".
CCLK
I
Control Data Clock Pin in Serial Mode and I2C pin = "L"
27
SCL
I
Control Data Clock Pin in Serial Mode and I2C pin = "H"
CSN
I
Chip Select Pin in Serial Mode and I2C pin = "L".
28
TEST
I
This pin should be connected to DVSS in Serial Mode and I2C pin = "H".
29
SDTIA1
I
Audio Serial Data Input A1 Pin
30
SDTIA2
I
Audio Serial Data Input A2 Pin
31
SDTIA3
I
Audio Serial Data Input A3 Pin
32
SDTIB
I
Audio Serial Data Input B Pin
33
HVDD -
HP Power Supply Pin, 4.5V
5.5V
34
HVSS
-
HP Ground Pin, 0V
35
HPR
O
HP Rch Output Pin
36
HPL
O
HP Lch Output Pin
37 MUTET
-
HP Common Voltage Output Pin
1
F capacitor should be connected to HVSS externally.
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