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Электронный компонент: AK7746VT

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[ASAHI KASEI]
[AK7746]

[MS0369-E00]
- 1 -
2004/12

The AK7746 is a highly integrated audio processor, including 5 A/D channels, an input mux that can select 2 stereo pairs
from 8 stereo inputs, and an on-chip DSP. High quality analog performance is provided by the ADC's achieving 98dB
(48kHz) dynamic range. The A/D supports sampling frequencies from 8kHz to 96kHz. The AK7746 includes 72kbits of
SRAM for audio delay that is suitable for simulated surround functions and speaker compensation. The programmable
DSP allows up to 4608 execution lines per audio sample cycle at 8kHz, 768 lines at 48kHz, or 384 lines at 96kHz with
multiple functions per line. The AK7746 can be used to implement complete sound field control, such as echo, 3D,
parametric equalization, etc. It is packaged in a 64-lead LQFP.
1.
General
Description
2. Features
DSP:
-
Word length:
24-bit (Data RAM)
-
Instruction cycle time:
27ns (768fs, fs=48kHz )
-
Multiplier:
24 x 16
40-bit
-
Divider:
24 / 24
16-bit or 24-bit
-
ALU:
34-bit arithmetic operation (Overflow margin: 4bit)
-
24-bit arithmetic and logic operation
-
Shift+Register:
1, 2, 3, 4, 6, 8 and 15 bits shifted left
1, 2, 3, 4, 8 and 15 bits shifted right
(Other numbers in parentheses are restricted.
Provided with indirect shift function)
-
Program RAM:
768 x 32-bit
-
Coefficient RAM:
1024 x 16-bit
-
Data
RAM:
256
x
24-bit
-
Offset RAM:
48 x 13-bit
(6144 x 12-bit / 3072 x 24-bit / 4096 x 12-bit + 1024 x 24-bit )
-
Internal
Memory:
72kbit
SRAM
-
Sampling frequency:
8kHz to 96kHz
-
Serial interface port for micro-controller
-
Master clock:
768fs@48kHz ( generated by PLL from 256fs or 384fs )
-
Master/Slave operation
-
Serial signal input port ( 8(10) ch ):16/20/24-bit : Output port ( 8ch + 4ch ): 24-bit

ADC:
4 channels (2 channels 2 sets )
-
24-bit 64 x Over-sampling delta sigma
-
Sampling frequency:
8kHz to 96kHz
-
DR:
98dBA ( fs=48 kHz Full-differential Input )
-
S/N :
98dBA ( fs=48 kHz Full-differential Input )
-
S/(N+D) :
91dB ( fs= 48 kHz Full-differential Input )
-
Digital HPF (fc = 1Hz)
-
Single-ended or Full-differential Input
ADC:
Monaural 1 channel
-
24-bit 64x Over-sampling delta sigma
-
Sampling frequency:
8kHz to 96kHz
-
DR:
97dBA ( fs=48 kHz )
-
S/N :
97dBA ( fs=48 kHz )
-
S/(N+D) :
91dB ( fs= 48 kHz )
Other
-
External Jump pin:
3(maximum)
-
CRC error check function
-
LRCLK and BITCLK input and output for slave mode
-
Power
supply:
+3.3V
0.3V
-
Operating temperature range:
-40
C~85C
-
Package:
64pin LQFP (0.5mm pitch)
Audio DSP with 5-channel 24-bit ADC and Input Mux
AK7746
[ASAHI KASEI]
[AK7746]

[MS0369-E00]
- 2 -
2004/12
3. Block diagram
INIT_RESET
S_RESET
CKS1
PLL&DIVIDER
CONTROLLER
pull down
Hi-z
ctrl reg sw
@ RQ ="H"
SWQMD
CLKOE_N
L
RCL
K
_
I
SM
OD
E
LFLT
L
RCL
K
_
O
BITC
LK_
O
BITC
LK_
I
SDIN3/JX1
SDIN1/JX0
JX0
SDOUT4
SDOUT3
SDOUT2
SDOUT1
SDIN4
SDIN3
SDIN2
SDIN1
JX1
JX2
DSP
SDIN5
SDIN4/JX2
SWQ4
SWQ3
SWQ2
SWQ1
OUT4E_N
OUT3E_N
OUT2E_N
OUT1E_N
RQ
SCLK
SI
SO
RDY
2
4
VREF
2
2
2
2
2
2
2 2
ADC2
ADC1
ADCM
SDIN2
CKS0
A
SEL1[
2:
0]
A
SEL2[
2:
0]
OUTA2E N
OUTA1E_N
SWQM1
SWQM2
SWSDIN1
SWSDIN2 N
SWAD1 N
JX0_E
SWSDIN3 N
SWSDIN4 N
SWADM3_N
SWADM2_N
JX1_E
JX2_E
DRDY
CS
3
3
XTI
XTO
CLKO
SDOUT1
SCLK
SO
SDOUT4
SDOUT3
SDOUT2
SI
RQ
RDY
SDOUTA2
SDOUTA1
DRDY
CS
AVSS
VREFL
VCOM
VREFH
AVDD
BVSS
DVDD
DVSS
TESTI
A
INM
A
INL+
,AINR+
A
I
NL
-,A
I
NR-
AIN
L2,
AIN
R
2
A
INL3,
A
INR3
A
INL5,
A
INR5
A
INL6,
A
INR6
A
INL7,
A
INR7
A
INL8,
A
INR8
A
INL4,
A
INR4
This block diagram is a simplified illustration of the AK7746; it is not a circuit diagram.
Ctrl reg SW describes default setting.
[ASAHI KASEI]
[AK7746]

[MS0369-E00]
- 3 -
2004/12
AK7746 DSP Block diagram
CP0,CP1
CRAM
1024w
16bit
DP0,DP1
DRAM
256w
24bit
MPX16
MPX24
OFRAM
48w
13bit
X
Multiply
16bit
24bit 40bit
Micon I/F
Control
PRAM
768w
32bit
DEC
PC
Stack : 1level
MU
SHIF
A
AL
34bit
Overflow Margin: 4bit
DR0 3
Over Flow Data
Generator
Division
24
2424or16
Peak Detector
TMP 8
24bit
Serial I/F
CBUS(16bit)
DBUS(24bit)
40bit
24bit
34bit
34bit
24bit
2
24bit
SDOUT4
DLRA
6kw
12bit or 3kw 24bit
PTMP(LIFO)
6
24bit
DP0,DP1
4kw
12bit & 1kw 24bit
CMP(Compress & Expand)
2
24/20/16bit
2
24/20/16bit
SDIN3
2
24/20/16bit
2
24/20/16bit
SDIN1
SDIN2
SDIN4
2
24bit
SDOUT3
2
24bit
SDOUT2
2
24bit
SDOUT1
Y
DBUS
B
2
24/bit
SDIN5
[ASAHI KASEI]
[AK7746]

[MS0369-E00]
- 4 -
2004/12
4. Description of Input/Output Pins
(1) Pin layout
AVDD
AI
NL2
AVDD
VREFH
VCOM
(TOP VIEW)
64pin LQFP
DVDD
SDOUTA2
AINL7
DVSS
AVSS
AINR7
AINL6
AINR6
AINR
3
AINR
4
AI
NL4
AINR
2
AI
NM
Note) *** is internal pull-down pin.
17
28
19
18
21
20
23
22
25
24
26
27
2
1
7
6
5
4
3
11
10
9
8
12
45
44
43
42
41
39
40
47
46
37
38
48
60
58
59
56
57
54
55
63
53
61
62
64
AINR8
XTO
XTI
LFLT
SDOUT1
SI
RQ
AI
NL3
AINL-
AINR
+
DVDD
DVSS
15
14
13
16
AINL8
32
29
30
31
35
36
33
34
52
50
51
49
AINR-
AVSS
VREFL
SDOUT2
AINL+
CLKO
SO
SDOUT3
RDY
INIT_RESET
SDIN4/JX2
SDIN3/JX1
SDIN2
SDIN1/JX0
LRCLK_O
DVDD
DVSS
AINR5
AINL5
SCLK
SDOUT4
BVSS
CKS0
BIT
C
LK_O
SMODE
LRCLK_I
BIT
C
LK_I
TESTI
S_RESET
CKS1
DRDY
CS
SDOUTA1
[ASAHI KASEI]
[AK7746]

[MS0369-E00]
- 5 -
2004/12
(2) Pin function
Pin No
Pin name
I/O
Function Classification
1 AINR5 I
ADC1 or ADC2 Rch single ended analog input 5
2 AINL5 I
ADC1 or ADC2 Lch single ended analog input 5
3 AINR6 I
ADC1 or ADC2 Rch single ended analog input 6
4 AINL6 I
ADC1 or ADC2 Lch single ended analog input 6
5 AINR7 I
ADC1 or ADC2 Rch single ended analog input 7
6 AINL7 I
ADC1 or ADC2 Lch single ended analog input 7
7 AINR8 I
ADC1 or ADC2 Rch single ended analog input 8
8 AINL8 I
ADC1 or ADC2 Lch single ended analog input 8
Analog input
9 BVSS -
Analog ground (Silicon base ground level)
Connect with AVSS pin
Analog Power supply
10 DVSS -
Digital Ground 0.0V
11 DVDD -
Digital power supply 3.3V(typ)
Digital Power supply
12
CS
I
Chip select pin for Microcomputer interface. (Internal pull-down)
Normaly leave OPEN or connect with DVSS.
CS ="H" : SI can not input, SO,RDY,DRDY = Hi-Z.
13
RQ
I
Write request pin for Microcomputer interface.
RQ ="L" : Microcomputer interface enable.
For run-time data read out: RQ ="H".
When Microcomputer interface is not used or during initial reset, leave
RQ ="H".
14
SI
I
Serial data input and serial data output control pin for Microcomputer
interface.
When SI is not used, leave SI="L".
15 SCLK I
Serial data clock pin for Microcomputer interface.
When SCLK is not used, leave SCLK="H".
16 SO O
Serial data output pin for Microcomputer interface.
CS ="H" : SO = Hi-Z.
17 RDY O
Data write ready output pin for Microcomputer interface.
CS ="H" : RDY = Hi-Z.
18 DRDY O
Output data ready pin for Microcomputer interface.
CS ="H" : DRDY = Hi-Z.
Microcomputer
Interface
19
INIT_RESET
I Reset pin ( for initialization )
Used for initialization of the AK7746. When changing CKS1 or CKS0 and
changing XTI input frequency, this pin setting is necessary.
20
S_RESET
I System Reset pin
Reset
21 SDIN4/JX2 I
DSP serial data input pin / External condition jump pin
(Internal pull-down )
* Compatible with MSB justified 24 bits / LSB justified 24,20 and 16 bits
* It can change its function as a conditional jump pin JX2 by control register
setting (JX2_E).
Digital section
Serial input data /
Conditional input
22 SDIN3/JX1 I
DSP serial data input pin / External condition jump pin
(Internal pull-down )
* Compatible with MSB justified 24 bits / LSB justified 24,20 and 16 bits
* It can change its function as a conditional jump pin JX1 by control register
setting (JX1_E).
Digital section
Serial input data /
Conditional input