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Электронный компонент: AK7750VT

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[ASAHI KASEI]
[AK7750]
[MS0296-E-00] 1
2005/03


General Description
The AK7750 is a highly integrated Audio Digital Signal Processor with a stereo audio codec in one chip.
The AK7750 combines an on-chip DSP and an ARM7 processor that can be used to create Echo
Cancellation (EC) and Noise Cancellation (NC) functions. These functions make the AK7750 a perfect
choice for hands-free phones that require suppressing acoustic echo and noise. Voice quality and noise
suppression levels can be precisely adjusted by externally setting various parameters. Additionally, no
external Flash, ROM, or RAM is required as memories for Echo and Noise Cancellation are integrated on-
chip.

By using an external microprocessor to change algorithms, the AK7750 can be used in other audio
applications including sound field enhancements like surround, volume control, parametric equalizer and
speaker compensation. These functions are simplified by the AK7750 through the integration of 64K bit
delay data RAM, a high-performance audio Codec with sample rates from 8 KHz ~ 48 KHz, and 8-
channels of Digital Audio input / output.

What's more, the latest Surround Decoders can be also be implemented by using the certified algorithms
from various technology partners.
Features
[DSP Block]
Data Word Length: 24 bit
Machine Cycle: 27.1 ns (fastest) (768fs at 48 KHz)
Number of Steps: 768 steps max. at fs = 48 KHz
4608 steps max. at fs = 8 KHz
192 steps max. at fs = 192 KHz
Multiply: 24 x 16 -> 40 bit (enables double precision operation)
Division: 24 / 24 -> 24 bit or 16 bit
ALU: 34 bit arithmetic operation (overflow margin 4 bits)
24 bit arithmetic & logic operations
Shift: 1,2,3,4,6,8,15 Bit Left Shift with indirect shift function
1,2,3,4,8,14,15 bit Right Shift with indirect shift function
Program RAM (PRAM): 768 words x 32 bit
Coefficient RAM (CRAM): 1024 words x 16 bit
Data RAM (DRAM): 256 words x 24 bit
Offset RAM (OFRAM): 48 words x 12 bit
Delay RAM (DLRAM): 64K bits (following 3 types are selectable):
- 1K words 24 bit
- 1K words 24 bit & 2K words 16 bit (limited pointer capability)
- 4kword 16bit
Data Compression/Expansion circuits for 16 bit data handling are integrated on-chip
(Dynamic-range: 23 bit equivalent, S/N+D: 15 bit equivalent (FS)).
- In Hands-free mode, Delay RAM cannot be used.
Registers: 34 bits x 4 (ACC) [for ALU]
24 bit x 8 (TMP) [for DBUS Interface]
24 bit x 6 stage stacks (PTMP) [for DBUS Interface]
On-chip ARM7TDMI Processor:

Audio DSP with Built-in Hands-Free Phone Features
AK7750
[ASAHI KASEI]
[AK7750]
[MS0296-E-00] 2
2005/03
[ADC Block]
24 Bit 2 Channels (fs: 8 KHz ~ 48 KHz)
S/N+D: 91 dB (fs = 48 KHz)
Dynamic Range & S/N: 98 dBA (fs = 48 KHz)
On-chip DC offset canceling High Pass Filter

[DAC Block]
24 Bit 2 Channels
S/N+D: 86 dB (fs = 48 KHz)
Dynamic Range & S/N: 98 dBA (fs = 48 KHz)

[Input/Output Digital Interface]
Serial Data Input 8 channels (10 channels with on-board codec.)
Serial Data Output 6 channels (8 channels with on-board codec.)
Microprocessor Interface: 1 set of inputs and outputs

[General]
On-chip PLL
On-chip EEPROM (AK6512C, AK6514C) Interface
Single 3.3 V +/- 0.3 V Power Supply
Operating Temperature Range: -40
C to +85C
64-Pin LQFP
[ASAHI KASEI]
[AK7750]
[MS0296-E-00] 3
2005/03
Block Diagram

(1) Hands-Free Mode Diagram
D/A
D/A
iFFT
Spectrum
Subtraction
FFT
ARM Processor
Noise Canceller
Tel. Line
RAM
ROM
Digital
OUT(8ch)
P
I/F
EEPROM
Digital
IN(8ch)
PLL
Filter
+
Echo
Canceller
VAD
Filter
voice
SW
VAD
Tel. Line
DSP Block
I/F
Mic.
Speaker
Filter
Ctrl.
A/D
A/D
Block Diagram
(2) Audio Surround Mode Diagram
D/A
D/A
iFFT
Spectrum
Subtraction
FFT
ARM Processor
Noise Canceller
Audio_in
RAM
ROM
Digital
OUT(6(8))ch)
P
I/F
EEPROM
Digital
IN(8(10))ch)
PLL
Sound processing
(EQ,Surround,...)
VAD
voice
SW
Speaker
DSP Block
I/F
Audio_in
Speaker
A/D
A/D
OFF
Block Diagram
[ASAHI KASEI]
[AK7750]
[MS0296-E-00] 4
2005/03
(2) Total Block Diagram
1) EESEL = " L "
BITCLK_I
LRCLK_I
SMODE
BITCLK_O
LRCLK_O
LFLT
EESEL="L"
SDOUT1
SCLK
SO
RDY
DRDY
TESTI2
SDOUT4A
SDOUT3
SDOUT2
SI
RQ
REF
AINR+ AINR-
AOUTL
AOUTR
VCOM VREFH
VREFL
ADC
SDATA_AD
DAC
SDATA_DA
SDIN3/JX2
OUT4E
JX0/SDIN5A
SDIN2
SDIN1
SDOUTH
SDINH
CK_RESET
JX0
SDOUT4
SDOUT3
SDOUT2
SDOUT1
SDIN4
SDIN3
SDIN2
SDIN1
JX1
JX2
DSP
HF
ARM
SWJX0_N
TESTI1
SWJX1
SWJX2
SWIA
SWQD
SWQ4
INIT_RESET
S_RESET
HF
CS
CKS0
CKS1
CKSX
PLL&DIVIDER
HFST_N
CONTROLLER
XTI
XTO
CLKO
EESI
EECK
EECS_N
EESO
EEADR
EEPIF
EEST
AVDD
AVSS
BVSS
DVDD
DVSS
HFST
HFST
SDIN5
SDIN4/JX1
pull down
Hi-z
ctrl reg sw
@ CS ="H"
OUT3E_N
OUT2E_N
OUT1E_N
The above shows a simplified AK 7750 block diagram. It does not necessarily show the circuit diagram.
[ASAHI KASEI]
[AK7750]
[MS0296-E-00] 5
2005/03
2) EESEL = " H "
SDOUT1
SCLK
SO
RDY/EESI
DRDY/EECK
TESTI2
EESEL="H"
SDOUT4A
SDOUT3
SDOUT2
SI
RQ
REF
AINL+
AINL-
AINR+
AINR-
AOUTL
AOUTR
VCOM VREFH
VREFL
ADC
SDATA_AD
DAC
SDATA_DA
SDIN3/JX2
OUT4E
JX0/SDIN5A
SDIN2
SDIN1
SDOUTH
SDINH
CK_RESET
JX0
SDOUT4
SDOUT3
SDOUT2
DRDY
SDIN4
SDIN3
SDIN2
SDIN1
JX1
JX2
DSP
HF
ARM
SWJX0_N
TESTI1
SWJX1
SWJX2
SWIA
SWQD
SWQ4
INIT_RESET
S_RESET
CKS0
CKS1
CKSX="H"
PLL&DIVIDER
HFST_N/EEST
CONTROLLER
XTI
XTO
CLKO
EESI
EECK
EEPIF
EEST
AVDD
AVSS
BVSS
DVDD
DVSS
RDY
HFST
SWEE
EECK_N
EESO
EEADR
SDOUT1
SDIN4/JX1
SDIN5
HFST
pull down
ctrl reg sw
HF
OUT3E_N
OUT2E_N
OUT1E_N
LRCLK
LFLT
BITCLK
SMODE
The above shows a simplified AK 7750 block diagram. It does not necessarily show the circuit diagram.