ASAHI KASEI

[AK8815/16]

MS0331-E-00

2004 / 08

AK8815/16

NTSC/PAL Digital Video Encoder

GENERAL DESCRIPTION

The AK8815/16 is a digital video encoder which is developed for portable apparatus applications such as cellular
phone etc.. ITU-R BT.601 level compatible Y, Cb,and Cr signals which correspond to square pixel are encoded
into either NTSC or PAL compatible composite video signal. Interface is made in HSYNC-, VSYNC- synchronized
slave-mode operation. It is controlled via a 4-wire serial interface.

FEATURES

· NTSC-M, PAL-B, D, G, H, I encoding
· Composite Video Output
· Y:Cb:Cr 4:2:2 Square Pixel Data Input
· H/V Slave Operation
· Y filtering: 2 x over-sampling
· C filtering: 4 x over-sampling
· 9-bit DAC
· Macrovision Copy Protection Rev. 7.1 * (only AK8815 )
· VBID ( CGMS-A ) Compatible
· WSS Compatible
· On-chip Quartz Crystal Oscillator circuit
· Clock: Square Pixel data rate 24.5454 MHz ( NTSC ), 29.50 MHz ( PAL )
· Device Control I / F : 4- wire Serial Bus Interface
· On-chip Color Bar Output
· Black Burst Output
· Internal Operating Voltage: 2.7 V ~ 3.3 V
· supplying Interface Power Supply ( 1.6 V ~ 2.0 V or 2.7 V ~ 3.3 V )
· Power-down function
· Monolithic CMOS
· 57 pin FBGA ( 5 mm sq ) ( lead-free package )

(*Note) This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other
intellectual rights. The use of Macrovision's copy protection technology in the device must be authorized by
Macrovision and is intended for home and other limited pay-per -view use only, unless otherwise authorized in
written by Macrovision. Reverse engineering or disassembly is prohibited.

ASAHI KASEI

[AK8815/16]

MS0331-E-00

2004 / 08

BLOCK DIAGRAM

VREF

Generator

AVDD AVSS

DVDD

DVSS

VREF

IREF

XTI/CLKIN

pu
t D
a
ta

Co
n

t
rol

y
nc

izat
ion
C

n
t
ro

SubCarrier

Generator

Chroma

LPF Filter

(x 2 Interpolator)

VIDEOOUT

SDO

VSYNC

HSYNC

SCLK

CS SDI

RSTN PDN

Color Bar &

Background

Color Control

Cb/Cr

LPF Filter

(x 2 Interpolator)

LPF Filter

(x 2 Interpolator)

SYNC

Generator

9-bit

DAC

D[7:0

]

CLKOUT

XTO

u-p I/F

Timing Controller

CLK

Generator

CLKINV

Sin

Cos

PVDD1 PVSS1

PVDD2

PVSS2

CLKMD

VBID & WSS

Macrovision

UD[4:0]

TEST

Logic

TEST ATPG

XVDD

ASAHI KASEI

[AK8815/16]

MS0331-E-00

2004 / 08

PIN FUNCTIONAL DESCRIPTION (preliminary)

No.

Pin Name

I/O

Function

A7 XTI/CLKIN I

Quartz crystal resonator connection pin ( to be grounded via a 18 pF capacitor as shown
in the recommended circuit ).
NTSC: 24.5454 MHz / PAL: 29.50 MHz
Hi-Z input is acceptable to this pin at PDN = L.
Input from an external crystal oscillator should be connected to this pin.

B6 XTO

Quartz crystal resonator connection pin ( to be grounded via a 22 pF capacitor as shown
in the recommended circuit ).
NTSC: 25.5454 MHz / PAL: 29.50 MHz
DVSS level is output on this pin at PDN = L.

B5 CLKMD

Clock Mode setting pin. Should be connected to either DVDD or DGND.
GND connection: when a crystal resonator is used
XVDD connection: when an external crystal oscillator is used

B9 CLKOUT

Clock output pin. NTSC: 24.5454 MHz / PAL: 29.50 MHz
This becomes Hi-Z output at PDN =L.

B7 CLKINV

"L " : data is latched with rising edge.
"H" : data is latched with falling edge.
Internal clock is inverted (internal operation timing edge is inverted. CLKOUT is not
affected). Connect to either DVDD or DGND.

J6 PDN

Power Down Pin. After returning from PD mode to normal operation, RESET Sequence
should be done to AK8815/16.
"L "(GND level): Power-down
"H ": normal operation

J5 RSTN

Reset input pin. In order to initialize the device , an initialization must be made in

accordance with the reset sequence.
"L " : reset
"H " : reset
Hi-Z input is acceptable to this pin at PDN = L.

J4 SCLK

Serial Data clock input pin. 15 MHz ( max )
Hi-Z input is acceptable to this pin at PDN = L.

H4 SDI

Serial Data input pin.
Hi-Z input is acceptable to this pin at PDN = L.

H3 SDO

Serial Data output pin.
This becomes high output at PDN = L.
This pin interfaces one-to-one with a controller through a dedicated pin.

H5 CS

Serial Data Chip Enable signal input pin.
This pin interfaces one-to-one with a controller through a dedicated pin.
L : disabled condition ( un-selected )
H : enabled condition ( selected )
Hi-Z input is acceptable to this pin at PDN = L.

H8 D7

Data Video Signal input pin (MSB).
Hi-Z input is acceptable to this pin at PDN = L.

G8 D6