ASAHI KASEI
[AK93C45B/55B/65B/75B]
DAM04E-01
1999/10
- 1 -
AK93C45B / 55B / 65B / 75B
1K / 2K / 4K / 8Kbit Serial CMOS EEPROM
Features
ADVANCED CMOS EEPROM TECHNOLOGY
READ/WRITE NON-VOLATILE MEMORY
WIDE VCC OPERATION
Vcc = 1.8V
5.5V
AK93C45B
1024 bits, 64
16 organization
AK93C55B
2048 bits, 128
16 organization
AK93C65B
4096 bits, 256
16 organization
AK93C75B
8192 bits, 512
16 organization
SERIAL INTERFACE
- Interfaces with popular microcontrollers and standard microprocessors
LOW POWER CONSUMPTION
- 0.8
A Max. Standby
HIGH RELIABILITY
-Endurance
: 100K cycles
-Data Retention
: 10 years
Automatic address increment (READ)
Automatic write cycle time-out with auto-ERASE
Busy/Ready status signal
Software controlled write protection
IDEAL FOR LOW DENSITY DATA STORAGE
- Low cost, space saving, 8-pin package (MSOP)
Block Diagram
ASAHI KASEI
[AK93C45B/55B/65B/75B]
DAM04E-01
1999/10
- 2 -
General Description
The AK93C45B/55B/65B/75B is a 1024/2048/4096/8192-bit serial CMOS EEPROM divided into
64/128/256/512 registers of 16 bits each.
The AK93C45B/55B/65B/75B has 4 instructions such as READ, WRITE, EWEN and EWDS. Those
instructions control the AK93C45B/55B/65B/75B.
The AK93C45B/55B/65B/75B can operate full function under wide operating voltage range from 1.8V to 5.5V.
The charge up circuit is integrated for high voltage generation that is used for write operation.
A serial interface of AK93C45B/55B/65B/75B, consisting of chip select (CS), serial clock (SK), data-in (DI)
and data-out (DO), can easily be controlled by popular microcontrollers or standard microprocessors.
AK93C45B/55B/65B/75B takes in the write data from data input pin (DI) to a register synchronously with rising
edge of input pulse of serial clock pin (SK). And at read operation, AK93C45B/55B/65B/75B takes out the
read data from a register to data output pin (DO) synchronously with rising edge of SK.
The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data output or Busy/Ready
signal output.
Software and Hardware controlled write protection
When Vcc is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the
ERASE/WRITE disable state, execution of WRITE instruction is disabled. Before WRITE instruction is
executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS
instruction is executed or Vcc is removed from the part.
Execution of a read instruction is independent of both EWEN and EWDS instructions.
The PE is internally pulled up to VCC. If the PE is left unconnected, the part will accept WRITE, EWEN and
EWDS instructions.
AK93C55B/65B/75B
Busy/Ready status signal
After a write instruction, the DO output serves as a Busy/Ready status indicator. After the falling edge of the
CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status of the chip if the CS is
brought high after a minimum of 250ns (Tcs). DO=logical "0" indicates that programming is still in progress.
DO=logical "1" indicates that the register at the address specified in the instruction has been written with the
new data pattern contained in the instruction and the part is ready for a next instruction.
The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes
into a high impedance state.
The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part.
Type of Products
Model
Memory size
Temp.Range
Vcc
Package
AK93C45BH
1Kbits
-40
C
85
C
1.8V
5.5V
8pin Plastic MSOP
AK93C55BH
2Kbits
-40
C
85
C
1.8V
5.5V
8pin Plastic MSOP
AK93C65BH
4Kbits
-40
C
85
C
1.8V
5.5V
8pin Plastic MSOP
AK93C75BH
8Kbits
-40
C
85
C
1.8V
5.5V
8pin Plastic MSOP
ASAHI KASEI
[AK93C45B/55B/65B/75B]
DAM04E-01
1999/10
- 3 -
Pin arrangement
Pin Name
Function
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
PE
Program Enable
GND
Ground
Vcc
Power Supply
NC
Not Connected
(Note) The PE is internally pulled up to VCC ( R = typ.2.5M
, VCC=5V ).
ASAHI KASEI
[AK93C45B/55B/65B/75B]
DAM04E-01
1999/10
- 4 -
Functional Description
The AK93C45B/55B/65B/75B has 4 instructions such as READ, WRITE, EWEN and EWDS. A valid
instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the desired memory Address
location.
The CS pin must be brought low for a minimum of 250ns (Tcs) between each instruction when the instruction
is continuously executed.
Instruction
Start
Bit
Op
Code
Address
Data
Comments
READ
1
10
A5-A0
D15-D0
Reads data stored in memory, at specified address.
WRITE
1
01
A5-A0
D15-D0
Writes register.
EWEN
1
00
11XXXX
Write enable must precede all programming modes.
EWDS
1
00
00XXXX
Disables all programming instructions.
WRAL
1
00
01XXXX
D15-D0
Writes all registers.
X: Don't care
table 1. Instruction Set for the AK93C45B
Instruction
Start
Bit
Op
Code
Address
Data
Comments
READ
1
10
X A6-A0
D15-D0
Reads data stored in memory, at specified address.
WRITE
1
01
X A6-A0
D15-D0
Writes register.
EWEN
1
00
11XXXXXX
Write enable must precede all programming modes.
EWDS
1
00
00XXXXXX
Disables all programming instructions.
WRAL
1
00
01XXXXXX
D15-D0
Writes all registers.
X: Don't care
table 2. Instruction Set for the AK93C55B
Instruction
Start
Bit
Op
Code
Address
Data
Comments
READ
1
10
A7-A0
D15-D0
Reads data stored in memory, at specified address.
WRITE
1
01
A7-A0
D15-D0
Writes register.
EWEN
1
00
11XXXXXX
Write enable must precede all programming modes.
EWDS
1
00
00XXXXXX
Disables all programming instructions.
WRAL
1
00
01XXXXXX
D15-D0
Writes all registers.
X: Don't care
table 3. Instruction Set for the AK93C65B
Instruction
Start
Bit
Op
Code
Address
Data
Comments
READ
1
10
XA8-A0
D15-D0
Reads data stored in memory, at specified address.
WRITE
1
01
XA8-A0
D15-D0
Writes register.
EWEN
1
00
11XXXXXXXX
Write enable must precede all programming modes.
EWDS
1
00
00XXXXXXXX
Disables all programming instructions.
WRAL
1
00
01XXXXXXXX D15-D0
Writes all registers.
X: Don't care
table 4. Instruction Set for the AK93C75B
(Note)
The WRAL instruction are used for factory function test only.
User can't use the WRAL instruction.
The AK93C45B/55B/65B/75B perceives the start bit in the logic"1" and also "01".
ASAHI KASEI
[AK93C45B/55B/65B/75B]
DAM04E-01
1999/10
- 5 -
Write
The write instruction is followed by 16 bits of data to be written into the specified address. After the last bit of
data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This
falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of
the chip if the CS is brought high after a minimum of 250ns (Tcs). DO=logical "0" indicates that programming
is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has
been written with the new data pattern contained in the instruction and the part is ready for a next instruction.
WRITE (AK93C45B)
*Address bit A7 becomes a "don't care" for AK93C55B.
WRITE (AK93C55B/65B)
WRITE (AK93C75B)
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