FEATURES
I High-Speed Source Drivers
I 60 V Source Outputs
I To 3.3 MHz Data Input Rate
I Low Output-Saturation Voltages
I Low-Power CMOS Logic and Latches
BiMOS II 20-BIT SERIAL-INPUT, LATCHED
SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
The UCN5812AF/EPF combine a 20-bit CMOS shift register, data
latches, and control circuitry with high-voltage bipolar source drivers and
active DMOS pull-downs for reduced supply current requirements. Although
designed primarily for vacuum-fluorescent displays, the high-voltage, high-
current outputs also allow them to be used in other peripheral power driver
applications. They are improved versions of the original UCN5812A/EP.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V supply, they will operate to at
least 3.3 MHz. At 12 V, higher speeds are possible. Especially useful for
inter-digit blanking, the BLANKING input disables the output source drives
and turns on the DMOS sink drivers. Use with TTL may require the use of
appropriate pull-up resistors to ensure an input logic high.
A CMOS serial data output enables cascade connections in applications
requiring additional drive lines. Similar devices are available as the
UCN5810AF/LWF (10 bits), UCN5811A (12 bits), and UCN5818AF/EPF
(32 bits).
The output source drivers are high-voltage pnp-npn Darlingtons with a
minimum breakdown of 60 V and are capable of sourcing up to 40 mA. The
DMOS active pull-downs are capable of sinking up to 15 mA.
The UCN5812AF is supplied in a 28-pin dual in-line plastic package with
0.600" (15.24 mm) row spacing. For surface mounting, the UCN5812EPF is
furnished in 28-lead plastic chip carrier (quad pack) with 0.050"(1.22 mm)
centers. Copper lead-frames, reduced supply current requirements and lower
output saturation voltages, allow continuous operation, with all outputs
sourcing 25 mA, of the UCN5812AF over the operating temperature range,
and the UCN5812EPF up to +75
C. All devices are also available for opera-
tion between -40
C and +85C. To order, change the prefix from `UCN' to
`UCQ'.
Always order by complete part number, e.g.,
UCN5812AF .
Data Sheet
26182.26B
I Active DMOS Pull-Downs
I Reduced Supply Current
Requirements
I Improved Replacement
for TL5812
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25
C
Logic Supply Voltage, V
DD
..................... 15 V
Driver Supply Voltage, V
BB
.................... 60 V
Continuous Output Current Range,
I
OUT
................................. -40 to +15 mA
Input Voltage Range,
V
IN
........................ -0.3 V to V
DD
+ 0.3 V
Package Power Dissipation, P
D
(UCN5812AF) ........................... 3.12 W*
(UCN5812EPF) ........................ 1.92 W
Operating Temperature Range,
T
A
.................................. -20
C to +85
C
Storage Temperature Range,
T
S
................................ -55
C to +150
C
* Derate at rate of 25 mW/
C above T
A
= +25
C
Derate at rate of 15 mW/
C above T
A
= +25
C
Caution: Allegro CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Note that the UCN5812AF (dual in-line package)
and UCN5812EPF (PLCC package) are electri-
cally identical and share a common terminal
number assignment.
UCN5812EPF
2
3
4
5
6
7
8
9
12
13
14
15
16
28
1
V
DD
Dwg. PP-059-1
OUT
10
OUT
20
OUT
11
OUT
19
REGISTER
LATCHES
V
BB
CLOCK
ST
CLK
26
27
22
23
24
25
SERIAL
DATA OUT
LOAD
SUPPLY
SERIAL
DATA IN
10
11
STROBE
GROUND
LOGIC
SUPPLY
19
20
21
BLANKING
17
18
OUT
9
OUT
1
OUT
2
OUT
8
OUT
18
OUT
12
LATCHES
REGISTER
5812-F
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
TRUTH TABLE
Serial
Shift Register Contents
Serial
Latch Contents
Output Contents
Data
Clock
Data
Strobe
Input
Input
I
1
I
2
I
3
...
I
N-1
I
N
Output
Input
I
1
I
2
I
3
...
I
N-1
I
N
Blanking
I
1
I
2
I
3
...
I
N-1
I
N
H
H
R
1
R
2
...
R
N-2
R
N-1
R
N-1
L
L
R
1
R
2
...
R
N-2
R
N-1
R
N-1
X
R
1
R
2
R
3
...
R
N-1
R
N
R
N
X
X
X
...
X
X
X
L
R
1
R
2
R
3
...
R
N-1
R
N
P
1
P
2
P
3
...
P
N-1
P
N
P
N
H
P
1
P
2
P
3
...
P
N-1
P
N
L
P
1
P
2
P
3
...
P
N1
P
N
X
X
X
...
X
X
H
L
L
L
...
L
L
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
Dwg. No. 12,649A
Serial Data present at the input is transferred
to the shift register on the logic "0" to logic "1"
transition of the CLOCK input pulse. On succeed-
ing CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The latches
will continue to accept
new data as long as the STROBE is held high.
Applications where the latches are bypassed
(STROBE tied high) will require that the
BLANKING input be high during serial data
entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
E F
CLOCK
DATA IN
STROBE
BLANKING
OUT
N
A D
B
C
G
TIMING REQUIREMENTS
(T
A
= +25
C,V
DD
= 5 V, Logic Levels are V
DD
and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 300 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
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