SERIAL

DATA OUT

SERIAL

DATA IN

OUTPUT

ENABLE

LOGIC

SUPPLY

STROBE

LOGIC

GROUND

CLOCK

CLK

SUB

POWER

GROUND

SHIFT REGISTER

LATCHES

OUT

Dwg. PP-026A

OUT

BiMOS II 8-BIT SERIAL-INPUT,

LATCHED DRIVERS

Always order by complete part number, e.g., UCN5821A .

Data Sheet

26185.12E

5821

AND

5822

Note the DIP package and the SOIC package are
electrically identical and share common terminal
number assignments.

A merged combination of bipolar and MOS technology gives

these devices an interface flexibility beyond the reach of standard
logic buffers and power driver arrays. The UCN5821A,
UCN5821LW, UCN5822A, and UCN5822LW each have an
eight-bit CMOS shift register and CMOS control circuitry, eight
CMOS data latches, and eight bipolar current-sinking Darlington
output drivers. The UCN5821A/LW and UCN5822A/LW are
identical except for rated output voltage.

BiMOS II devices have much higher data-input rates than the

original BiMOS circuits. With a 5 V logic supply, they will
typically operate at better than 5 MHz. With a 12 V supply,
significantly higher speeds are obtained. The CMOS inputs are
compatible with standard CMOS and NMOS logic levels. TTL
circuits may require the use of appropriate pull-up resistors. By
using the serial data output, the drivers can be cascaded for
interface applications requiring additional drive lines.

The UCN5821/22A are furnished in a standard 16-pin plastic

DIP; the UCN5821/22LW are in a 16-lead wide-body SOIC for
surface-mount applications. The UCN5821A is also available for
operation from -40

°C to +85°C. To order, change the prefix from

`UCN' to `UCQ'.

FEATURES
I To 3.3 MHz Data Input Rate
I CMOS, NMOS, TTL Compatible
I Internal Pull-Down Resistors
I Low-Power CMOS Logic & Latches
I High-Voltage Current-Sink Outputs
I Automotive Capable

ABSOLUTE MAXIMUM RATINGS

at 25

C Free-Air Temperature

Output Voltage, V

OUT

UCN5821A & UCN5821LW ..... 50 V
UCN5822A & UCN5822LW ..... 80 V

Logic Supply Voltage, V

............. 15 V

Input Voltage Range,

.................. -0.3 V to V

+ 0.3 V

Continuous Output Current,

OUT

..................................... 500 mA

Package Power Dissipation, P

Package Code `A' .................. 2.1 W
Package Code `LW' ............... 1.5 W

Operating Temperature Range,

............................ -20

C to +85

Storage Temperature Range,

.......................... -55

C to +150

Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.

www.allegromicro.com

5821

AND

5822

8-BIT SERIAL-INPUT,
LATCHED DRIVERS

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

MOS

BIPOLAR

OUT

LOGIC

GROUND

STROBE

OUTPUT ENABLE
(ACTIVE LOW)

SERIAL
DATA OUT

Dwg. FP-013A

OUT

CLOCK

SERIAL

DATA IN

SERIAL-PARALLEL SHIFT REGISTER

LATCHES

LOGIC
SUPPLY

OUT

POWER
GROUND

SUB

FUNCTIONAL BLOCK DIAGRAM

TYPICAL INPUT CIRCUITS

Dwg. No. A-14,314

Dwg. EP-010-3

Dwg. EP-010-4A

STROBE &

OUTPUT

ENABLE

CLOCK &

SERIAL

DATA IN

Number of Outputs ON

UCN5821A Max. Allowable Duty Cycle

OUT

= 200 mA

at Ambient Temperature of

= 12 V)

90%

79%

72%

65%

57%

100%

90%

82%

74%

65%

100%

96%

86%

76%

100%

91%

100%

Number of Outputs ON

UCN5821LW Max. Allowable Duty Cycle

OUT

= 200 mA

at Ambient Temperature of

= 12 V)

67%

59%

54%

49%

43%

77%

68%

62%

56%

49%

90%

79%

72%

65%

57%

100%

95%

86%

78%

68%

100%

98%

86%

100%

TYPICAL OUTPUT DRIVER

OUT

SUB

7.2K

NOTE -- There is an indeterminate resistance between logic ground and power
ground. For proper operation, these terminals must be externally connected
together.

5821

AND

5822

8-BIT SERIAL-INPUT,

LATCHED DRIVERS

www.allegromicro.com

Limits

Characteristic

Symbol

Test Conditions

Min.

Max.

Units

Output Leakage

CEX

UCN5821A/LW, V

OUT

= 50 V

µA

Current

UCN5822A/LW, V

OUT

= 80 V

µA

UCN5821A/LW, V

OUT

= 50 V, T

= +70

°C

100

µA

UCN5822A/LW, V

OUT

= 80 V, T

= +70

°C

100

µA

Collector-Emitter

CE(SAT)

OUT

= 100 mA

1.1

Saturation Voltage

OUT

= 200 mA

1.3

OUT

= 350 mA, V

= 7.0 V

1.6

Input Voltage

IN(0)

0.8

IN(1)

= 12 V

10.5

= 5.0 V

3.5

Input Resistance

= 12 V

= 5.0 V

Supply Current

DD(ON)

One Driver ON, V

= 12 V

4.5

One Driver ON, V

= 10 V

3.9

One Driver ON, V

= 5.0 V

2.4

DD(OFF)

= 5.0 V, All Drivers OFF, All Inputs = 0 V

1.6

= 12 V, All Drivers OFF, All Inputs = 0 V

2.9

ELECTRICAL CHARACTERISTICS at T

= +25

C, V

= 5 V, (unless otherwise specified).

5821

AND

5822

8-BIT SERIAL-INPUT,
LATCHED DRIVERS

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

TIMING CONDITIONS

= 5.0 V, T

= +25

C, Logic Levels are V

and Ground)

Minimum Data Active Time Before Clock Pulse

(Data Set-Up Time) ....................................................................... 75 ns

Minimum Data Active Time After Clock Pulse

(Data Hold Time) ........................................................................... 75 ns

Minimum Data Pulse Width .............................................................. 150 ns

Minimum Clock Pulse Width ............................................................ 150 ns

Minimum Time Between Clock Activation and Strobe ....................... 30 ns

Minimum Strobe Pulse Width ........................................................... 100 ns

Typical Time Between Strobe Activation and

Output Transition .......................................................................... 1.0

TRUTH TABLE

Serial

Shift Register Contents

Serial

Latch Contents

Output Contents

Data

Clock

Data

Strobe

Output

Input

Input I

.............. I

Output

Input

.............. I

Enable

.............. I

.............. R

.............. X

.............. R

.............. P

.............. X

.............. H

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

Dwg. No. A-12,627

Serial Data present at the input is

transferred to the shift register on the
logic "0" to logic "1" transition of the
CLOCK input pulse. On succeeding
CLOCK pulses, the registers shift data
information towards the SERIAL DATA
OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge
of the CLOCK input waveform.

Information present at any register is

transferred to its respective latch when the
STROBE is high (serial-to-parallel con-
version). The latches will continue to
accept new data as long as the STROBE
is held high. Applications where the
latches are bypassed (STROBE tied high)
will require that the ENABLE input be
high during serial data entry.

When the ENABLE input is high, all

of the output buffers are disabled (OFF)
without affecting the information stored
in the latches or shift register. With the
ENABLE input low, the outputs are
controlled by the state of the latches.

CLOCK

DATA IN

STROBE

OUTPUT
ENABLE

OUT

5821

AND

5822

8-BIT SERIAL-INPUT,

LATCHED DRIVERS

www.allegromicro.com

NOTES: 1. Lead thickness is measured at seating plane or below.

2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor's option within limits shown.

0.014
0.008

0.300

BSC

Dwg. MA-001-16A in

0.430

MAX

0.280
0.240

0.210

MAX

0.070
0.045

0.015

MIN

0.022
0.014

0.100

BSC

0.005

MIN

0.150
0.115

0.775
0.735

0.355
0.204

7.62

BSC

Dwg. MA-001-16A mm

10.92

MAX

7.11
6.10

5.33

MAX

1.77
1.15

0.39

MIN

0.558
0.356

2.54

BSC

0.13

MIN

3.81
2.93

19.68
18.67

UCN5821A and UCN5822A

Dimensions in Inches

(controlling dimensions)

Dimensions in Millimeters

(for reference only)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 5821

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 5821