Data Sheet
26185.120
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
The A6595KA and A6595KLW combine an 8-bit CMOS shift
register and accompanying data latches, control circuitry, and DMOS
power driver outputs. Power driver applications include relays, sole-
noids, and other medium-current or high-voltage peripheral power
loads.
The serial-data input, CMOS shift register and latches allow direct
interfacing with microprocessor-based systems. Serial-data input rates
are over 5 MHz. Use with TTL may require appropriate pull-up
resistors to ensure an input logic high.
A CMOS serial-data output enables cascade connections in appli-
cations requiring additional drive lines. Similar devices with reduced
r
DS(on)
are available as the A6A595.
The A6595 DMOS open-drain outputs are capable of sinking up to
750 mA. All of the output drivers are disabled (the DMOS sink drivers
turned off) by the OUTPUT ENABLE input high.
The A6595KA is furnished in a 20-pin dual in-line plastic package.
The A6595KLW is furnished in a wide-body, small-outline plastic
package (SOIC) with gull-wing leads. Copper lead frames, reduced
supply current requirements, and low on-state resistance allow both
devices to sink 150 mA from all outputs continuously, to ambient
temperatures over 85
C.
FEATURES
I 50 V Minimum Output Clamp Voltage
I 250 mA Output Current (all outputs simultaneously)
I 1.3 Typical
r
DS(on)
I Low Power Consumption
I Replacements for TPIC6595N and TPIC6595DW
6595
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
LOGIC
GROUND
1
2
3
8
9
13
14
15
16
17
19
4
5
6
7
12
18
20
SERIAL
DATA OUT
SERIAL
DATA IN
LOGIC
SUPPLY
V
DD
STROBE
POWER
GROUND
CLOCK
CLK
ST
OUT
7
OUT
6
OUT
5
Dwg. PP-029-13
OUT
0
OUT
1
OUT
2
OUT
3
OUT
4
10
11
POWER
GROUND
POWER
GROUND
OUTPUT
ENABLE
OE
REGISTER
CLEAR
POWER
GROUND
LATCHES
REGISTER
REGISTER
LATCHES
CLR
Note that the A6595KA (DIP) and the A6595KLW (SOIC)
are electrically identical and share a common terminal
number assignment.
Always order by complete part number:
Part Number
Package
R
JA
R
JC
A6595KA
20-pin DIP
55
C/W
25
C/W
A6595KLW
20-lead SOIC
70
C/W
17
C/W
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25
C
Output Voltage, V
O
............................... 50 V
Output Drain Current,
Continuous, I
O
.......................... 250 mA*
Peak, I
OM
................................. 750 mA*
Peak, I
OM
....................................... 2.0 A
Single-Pulse Avalanche Energy,
E
AS
................................................. 75 mJ
Logic Supply Voltage, V
DD
.................. 7.0 V
Input Voltage Range,
V
I
................................... -0.3 V to +7.0 V
Package Power Dissipation,
P
D
........................................... See Graph
Operating Temperature Range,
T
A
................................. -40
C to +125
C
Storage Temperature Range,
T
S
................................. -55
C to +150
C
* Each output, all outputs on.
Pulse duration
100 s, duty cycle 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to damage if
exposed to extremely high static electrical charges.
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright 2000, Allegro MicroSystems, Inc.
FUNCTIONAL BLOCK DIAGRAM
50
75
100
125
150
2.5
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN
C
2.0
1.5
1.0
25
Dwg. GS-004A
SUFFIX 'LW
', R = 70
C/W
J
A
SUFFIX 'A', R = 55
C/W
J
A
LOGIC SYMBOL
2
G3
C2
SRG8
C1
R
1D
2
4
5
6
7
14
15
16
17
18
9
12
8
3
13
Dwg. FP-043
POWER
GROUND
Dwg. FP-013-5
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT
ENABLE
(ACTIVE LOW)
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
D-TYPE LATCHES
V
DD
LOGIC
SUPPLY
REGISTER
CLEAR
(ACTIVE LOW)
OUT
0
OUT
N
LOGIC
GROUND
POWER
GROUND
Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
www.allegromicro.com
TRUTH TABLE
Shift Register Contents
Serial
Latch Contents
Output Contents
Data
ClockData
Output
Input
Input
I
0
I
1
I
2
...
I
6
I
7
Output Strobe
I
0
I
1
I
2
...
I
6
I
7
Enable
I
0
I
1
I
2
...
I
6
I
7
H
H
R
0
R
1
...
R
5
R
6
R
6
L
L
R
0
R
1
...
R
5
R
6
R
6
X
R
0
R
1
R
2
...
R
6
R
7
R
7
X
X
X
...
X
X
X
--
R
0
R
1
R
2
...
R
6
R
7
P
0
P
1
P
2
...
P
6
P
7
P
7
P
0
P
1
P
2
...
P
6
P
7
L
P
0
P
1
P
2
...
P
6
P
7
X
X
X
...
X
X
H
H
H
H
...
H
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
SERIAL DATA OUT
LOGIC INPUTS
Dwg. EP-063-2
V
DD
OUT
DMOS POWER DRIVER OUTPUT
IN
Dwg. EP-010-15
V
DD
Dwg. EP-063-3
OUT
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, V
DD
............... 4.5 V to 5.5 V
High-Level Input Voltage, V
IH
............................
0.85V
DD
Low-level input voltage, V
IL
.................................
0.15V
DD
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Output Breakdown
V
(BR)DSX
I
O
= 1 mA
50
--
--
V
Voltage
Off-State Output
I
DSX
V
O
= 40 V
--
0.05
1.0
A
Current
V
O
= 40 V, T
A
= 125
C
--
0.15
5.0
A
Static Drain-Source
r
DS(on)
I
O
= 250 mA, V
DD
= 4.5 V
--
1.3
2.0
On-State Resistance
I
O
= 250 mA, V
DD
= 4.5 V, T
A
= 125
C
--
2.0
3.2
I
O
= 500 mA, V
DD
= 4.5 V (see note)
--
1.3
2.0
Nominal Output
I
ON
V
DS(on)
= 0.5 V, T
A
= 85
C
--
250
--
mA
Current
Logic Input Current
I
IH
V
I
= V
DD
= 5.5 V
--
--
1.0
A
I
IL
V
I
= 0, V
DD
= 5.5 V
--
--
-1.0
A
Logic Input Hysteresis
V
I(hys)
--
1.3
--
V
SERIAL-DATA
V
OH
I
OH
= -20
A, V
DD
= 4.5 V
4.4
4.49
--
V
Output Voltage
I
OH
= -4 mA, V
DD
= 4.5 V
4.1
4.3
--
V
V
OL
I
OL
= 20
A, V
DD
= 4.5 V
--
0.002
0.1
V
I
OL
= 4 mA, V
DD
= 4.5 V
--
0.2
0.4
V
Prop. Delay Time
t
PLH
I
O
= 250 mA, C
L
= 30 pF
--
650
--
ns
t
PHL
I
O
= 250 mA, C
L
= 30 pF
--
150
--
ns
Output Rise Time
t
r
I
O
= 250 mA, C
L
= 30 pF
--
7500
--
ns
Output Fall Time
t
f
I
O
= 250 mA, C
L
= 30 pF
--
425
--
ns
Supply Current
I
DD(OFF)
All inputs low
--
15
100
A
I
DD(ON)
V
DD
= 5.5 V, Outputs on
--
150
300
A
I
DD(fclk)
f
clk
= 5 MHz, C
L
= 30 pF, Outputs off
--
0.6
5.0
mA
Typical Data is at V
DD
= 5 V and is for design information only.
NOTE -- Pulse test, duration
100 s, duty cycle 2%.
ELECTRICAL CHARACTERISTICS at T
A
= +25
C, V
DD
= 5 V, t
ir
= t
if
10 ns (unless otherwise
specified).
6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are V
DD
and Ground)
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT
ENABLE
OUT
N
Dwg. WP-029-2
50%
SERIAL
DATA OUT
DATA
DATA
50%
50%
50%
C
A
B
D
E
LOW = ALL OUTPUTS ENABLED
p
t
DATA
50%
p
t
LOW = OUTPUT ON
HIGH = OUTPUT OFF
OUTPUT
ENABLE
OUT
N
Dwg. WP-030-2
DATA
10%
50%
PHL
t
PLH
t
HIGH = ALL OUTPUTS DISABLED
90%
f
t
r
t
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), t
su(D)
.......................................... 10 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), t
h(D)
.............................................. 10 ns
C. Clock Pulse Width, t
w(CLK)
............................................. 20 ns
D. Time Between Clock Activation
and Strobe, t
su(ST)
....................................................... 50 ns
E. Strobe Pulse Width, t
w(ST)
.............................................. 50 ns
F. Output Enable Pulse Width, t
w(OE)
................................ 4.5
s
NOTE Timing is representative of a 12.5 MHz clock.
Higher speeds are attainable.
Serial data present at the input is transferred to the shift
register on the rising edge of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information
towards the SERIAL DATA OUTPUT.
Information present at any register is transferred to the
respective latch on the rising edge of the STROBE input pulse
(serial-to-parallel conversion).
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
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