ALLIANCE

SEMICONDUCTOR

High Performance
32K

CMOS SRAM

AS7C256
AS7C256L

32K

8 CMOS SRAM (Common I/O)

LOGIC BLOCK DIAGRAM

FEATURES

· Organization: 32,768 words

8 bits

· High speed

10/12/15/20/25/35 ns address access time

3/3/4/5/6/8 ns output enable access time

· Low power consumption

Active:

660 mW max (10 ns cycle)

Standby:

11 mW max, CMOS I/O
2.75 mW max, CMOS I/O, L version

Very low DC component in active power

· 2.0V data retention (L version)

· Equal access and cycle times

· Easy memory expansion with CE and OE inputs

· TTL-compatible, three-state I/O

· 28-pin JEDEC standard packages

300 mil PDIP and SOJ

Socket compatible with 7C512 and 7C1024

330 mil SOIC

13.4 TSOP

· ESD protection > 2000 volts

· Latch-up current > 200 mA

SELECTION GUIDE

PIN ARRANGEMENT

256

128

ARRAY

(262,144)

INPUT BUFFER

A0
A1
A2
A3
A4
A5
A6

A14

I/O0

I/O7

Vcc

GND

COLUMN DECODER

ODE

CONTROL

CIRCUIT

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17

Vcc
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

A14
A12

A7
A6
A5
A4
A3
A2
A1
A0

I/O0
I/O1
I/O2

GND

7C25

16
15

AS7C256-02

AS7C256-01

7C256-10

7C256-12

7C256-15

7C256-20

7C256-25

7C256-35

Unit

Maximum Address Access Time

Maximum Output Enable Access Time

Maximum Operating Current

120

115

110

100

Maximum CMOS Standby Current

2.0

0.5

Vcc

A13

A11

A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

A14
A12

A7
A6
A5
A4
A3

I/O0

I/O1

I/O2

GND

DIP, SOJ, SOIC

TSOP 8

13.4

22
23
24
25
26
27
28
1
2
3
4
5
6
7

21
20
19
18
17
16
15
14
13
12
11
10

AS7C256

9
8

AS7C256
AS7C256L

The AS7C256 is a high performance CMOS 262,144-bit
Static Random Access Memory (SRAM) organized as
32,768 words

8 bits. It is designed for memory applica-

tions where fast data access, low power, and simple interfac-
ing are desired.

Equal address access and cycle times (t

, t

) of

10/12/15/20/25/35 ns with output enable access times (t

)

of 3/3/4/5/6/8 ns are ideal for high performance applica-
tions. A chip enable (CE) input permits easy memory
expansion with multiple-bank memory organizations.

When CE is HIGH the device enters standby mode. The
standard AS7C256 is guaranteed not to exceed 11 mW
power consumption in standby mode; the L version is guar-
anteed not to exceed 2.75 mW, and typically requires only
500

W. The L version also offers 2.0V data retention, with

maximum power consumption in this mode of 300

A write cycle is accomplished by asserting chip enable (CE)
and write enable (WE) LOW. Data on the input pins
I/O0-I/O7 is written on the rising edge of WE (write cycle 1)
or CE (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been
disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting chip enable (CE)
and output enable (OE) LOW, with write enable (WE)
HIGH. The chip drives I/O pins with the data word refer-
enced by the input address. When chip enable or output
enable is HIGH, or write enable is LOW, output drivers stay
in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and opera-
tion is from a single 5V supply. The AS7C256 is packaged
in all high volume industry standard packages.

FUNCTIONAL DESCRIPTION

Parameter

Symbol

Min

Max

Unit

Voltage on Any Pin Relative to GND

0.5

+7.0

Power Dissipation

1.0

Storage Temperature (Plastic)

stg

+150

Temperature Under Bias

bias

10 +85

DC Output Current

out

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Data

Mode

High Z

Standby (I

, I

SB1

)

High Z

Output Disable

out

Read

Write

Key: X = Don't Care, L = LOW, H = HIGH

ABSOLUTE MAXIMUM RATINGS

TRUTH TABLE

AS7C256
AS7C256L

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

4.5

5.0

5.5

GND

0.0

Input Voltage

2.2

0.5*

0.8

min = 3.0V for pulse width less than t

/2.

Parameter

Symbol Test Conditions

-10

-12

-15

-20

-25

-35

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Input Leakage
Current

= Max,

= GND to V

Output Leakage
Current

CE = V

, V

= Max,

out

= GND to V

Operating Power
Supply Current

CE = V

, f = f

max,

out

= 0 mA

120

115

110

100

115

110

105

Standby
Power Supply
Current

CE = V

, f = f

max

SB1

CE > V

0.2V, f = 0,

0.2V or

0.2V

2.0

0.5

Output Voltage

= 8 mA, V

= Min

0.4

= 4 mA, V

= Min

2.4

Parameter

Symbol

Signals

Test Conditions

Max

Unit

Input Capacitance

A, CE, WE, OE

= 0V

I/O Capacitance

I/O

= V

out

= 0V

RECOMMENDED OPERATING CONDITIONS

= 0°C to +70°C)

DC OPERATING CHARACTERISTICS

= 5V

10%, GND = 0V, T

= 0°C to +70°C)

CAPACITANCE

(f = 1 MHz, T

= Room Temperature, V

= 5V)

AS7C256
AS7C256L

Parameter

Symbol

-10

-12

-15

-20

-25

-35

Unit

Notes

Min Max Min Max Min Max Min Max Min Max Min Max

Read Cycle Time

Address Access Time

Chip Enable (CE) Access Time

ACE

Output Enable (OE) Access Time

Output Hold from Address Change

CE LOW to Output in Low Z

CLZ

4, 5

CE HIGH to Output in High Z

CHZ

4, 5

OE LOW to Output in Low Z

OLZ

4, 5

OE HIGH to Output in High Z

OHZ

4, 5

Power Up Time

4, 5

Power Down Time

4, 5

READ CYCLE

= 5V

10%, GND = 0V, T

= 0°C to +70°C)

3, 9

3, 6, 7, 9

TIMING WAVEFORM OF READ CYCLE 1

(Address Controlled)

AAAA

Address

out

Data Valid

3, 6, 8, 9

TIMING WAVEFORM OF READ CYCLE 2

(CE Controlled)

AAAA

Supply

Current

out

OLZ

ACE

CHZ

CLZ

50%

OHZ

AAAA

Data Valid

AAAA

AS7C256-04

AS7C256
AS7C256L

Parameter

Symbol

-10

-12

-15

-20

-25

-35

Unit

Notes

Min Max Min Max Min Max Min Max Min Max Min Max

Write Cycle Time

Chip Enable to Write End

Address Setup to Write End

Address Setup Time

Write Pulse Width

Address Hold From End of Write

Data Valid to Write End

Data Hold Time

4, 5

Write Enable to Output in High Z

4, 5

Output Active from Write End

4, 5

WRITE CYCLE

= 5V

10%, GND = 0V, T

= 0°C to +70°C)

10, 11

TIMING WAVEFORM OF WRITE CYCLE 1

(WE Controlled)

AAAA

Address

out

Data Valid

AS7C256-05

10, 11

TIMING WAVEFORM OF WRITE CYCLE 2

(CE Controlled)

AAAA

AAA

Address

out

Data Valid

AAAA

AAA

AS7C256-06

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 7C256-35

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 7C256-35