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6HOHFWLRQ#JXLGH

AS29F010-120

AS29F010-150

Unit

Maximum access time

120

150

Chip enable access time

120

150

Output enable access time

3LQ#DUUDQJHPHQW

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

WE
NC*
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3

A16
A15
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0
DQ1
DQ2

A14

A13

A11

OE
A10
CE
DQ7
DQ6
DQ5

A16
A15
A12

A7
A6
A5
A4

DQ0

DQ1

DQ2

DQ4
DQ3

1
2
3
4
5
6
7
8
9
10
11
12
13
14

32
31
30
29
28
27
26
25
24
23
22
21

20
19

15
16

18
17

A14

A13

A11

A10

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ0

DQ7

32-pin

PDIP

PLCC

TSOP

AS29F010

AS2

9F01

)HDWXUHV

· Organization: 128K × 8 bits
· Sector Erase architecture

- Four 32K × 8 sectors

· Single 5.0±0.5V power supply for read/write operations
· High speed 120/150 ns address access time
· Low power consumption:

- 30 mA maximum read current
- 50 mA maximum program current
- 1.5 mA maximum standby current
- 1 mA maximum standby current (low power)

· 10,000 write/erase cycle endurance

· JEDEC standard write cycle commands

- protects data from accidental changes

· Program/erase cycle end signals:

- Data polling
- DQ6 toggle

· Low V

write lock-out below 3.2V

· JEDEC standard packages and pinouts:

- 32-pin DIP
- 32-pin PLCC
- 32-pin TSOP

/RJLF#EORFN#GLDJUDP

CE
OE

Low V

detector

Program/erase

pulse timer

State

control

Command

Erase voltage

switch

Input/output

buffers

Program voltage

switch

Data
latch

Chip enable

Output enable

Logic

X-Decoder

Y-Gating

Y-Decoder

1,048,576 bit

Cell matrix

Addr

s
la

t
c

~DQ

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The AS29F010 is a high performance 1 megabit 5 volt-only Flash memory organized as 128K bytes of 8 bits each. It is divided into four
sectors of 32K bytes each. Each sector is separately erased and programmed without affecting data in the other sectors. All prog ram, erase,
and verify operations are 5-volt only, and require no external 12V supply pin. All required features for in-system programmability are
provided.

The AS29F010 provides high performance with a maximum access time of 120, or 150 ns. Chip Enable ( CE), Output Enable ( OE), and
Write Enable (WE) pins allow easy interface with the system bus.

Program, erase, and verify operations are controlled with an on-chip command register using a JEDEC standard Write State Machine
approach to enter commands. Each command requires four write cycles to be executed. Address and data are latched internally duri ng all
write, erase, and verify operations, and an internal timer terminates each command. The chip has a typical timer period of 200 µ s for all
commands but Erase, which has a typical period of 800 ms. Under nominal conditions, a sector can be completely programmed and verified
in less than 12 seconds. To program, erase, and verify a sector typically takes less than 18 seconds.

Data protection is provided by a low-V

lockout and by error checking in the Write State Machine. DATA polling and Toggle Bit modes are

used to show that the chip is executing a command when the AS29F010 is read during a write or erase operation. After Erase or P ogram
commands, Verify-1 and Verify-0 command modes ensure sufficient margin for reliable operation. (See command summary on page 5.)

The AS29F010 is packaged in 32-pin DIP, PLCC and TSOP packages with JEDEC standard pinouts for one megabit Flash memories.

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The array consists of 128K (131,072) bytes divided into four sectors of 32K bytes each. Addresses A15 and A16 select the four sectors:

The AS29F010 is shipped in the erased state with all bits set to 1. Programmed bits are set to 0. Data is programmed into the a ray one byte
at a time. All programmed bits remain set to 0 until the sector is erased and verified using the Sector Erase and Verify algorit hm. Erase returns
all bytes in a 32K sector to the erased state FFh, or all bits set to 1. Each sector is erased individually with no effect on the other sectors.

2SHUDWLQJ#PRGHV

The AS29F010 is controlled by a Write State Machine (WSM) that interprets and executes commands. At power-up the WSM is reset to
normal read mode. Once a command is initiated by writing data into the DQ pins with the WE pin, the WSM enters the command mode and
keeps the chip powered up until the command is finished. After the command is terminated by the internal timer, the WSM returns to the
normal read mode.

Sector

Address range

Address pins

Function

00000h07FFFh

A0A5

CA: Column addresses 003Fh

08000h0FFFFh

A6A14

RA: Row addresses 0001FFh

10000h17FFFh

A15A16

SA: Sector addresses 03h

18000h1FFFFh

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6

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Key: L =Low (<VIL); H = High (>VIH); Vh = 11.512.5V; X =Don't care

Read mode: Selected with CE and OE low, WE high. Data is valid tAA after addresses are stable, tCE after CE is low and tOE after OE is low.

Output disable: Part remains powered up; but outputs disabled with OE pulled high.

Standby: Part is powered down, and ICC reduced to 1.5 mA for TTL input levels (<1.0 mA for CMOS input levels).

Mfr. (manufacturer) code, Device code: Selected by A9 = 11.512.5V. When CE and OE are pulled low the outputs are enabled and a data byte is read out.
When A0 is pulled low the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high DOUT = 03h,04h, 06h, the
Alliance device codes for the AS29F010.

Write command: Selected by CE and WE pulled low, OE pulled high. Initiates command mode in the WSM and latches addresses and data into the chip. Once
a write command starts, the WSM stays in command mode until the command is completed or it times out. Addresses are latched on the falling edge of WE
and CE, whichever occurs later; data is latched on the rising edge o WE and CE, whichever occurs first. The WE signal is filtered to prevent spurious events
from being detected as write commands.

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All commands require four bus write cycles to execute. After four write cycles the command is executed until terminated by the i nternal
timer. For verify commands a read operation after Write

[4]

in a write command bus cycle reads out the data from the array. For manufacturer

and device code commands the ID code is read out. For other operations a read operation reads out a status byte on the outputs.

Errors a

nd timeout: Any of the following conditions sets the error flag.

· Any write command which does not match the sequence above for Write

{1]

. Write

{2]

, and Write

[3]

Any write cycle that follows more than 150 µs after the previous write cycle.

The command Data

[3]

in Write

[3]

has more than one bit set high. This indicates conflicting commands.

drops below V

LKO

during command execution.

Once the error flag is set, the AS29F010 times out and returns to normal Readmode. The error flag remains until it is cleared by a reset
command. The error flag can be read by executing a status command and reading the status byte.

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The Command Code table displays the bus cycles required for each command mode. Read delay is the minimum delay after Write

[4]

during

a write command bus cycle before a valid read may be executed. Timeout indicates the maximum delay before the WSM returns the
AS29F010 to normal mode. Erase has a longer timeout than the other modes. Status byte can be read almost immediately after a Write

[4]

, but

the verify commands require a 25 µs delay to read valid data.

Mode

Read

OUT

Output disable

High Z

Standby

High Z

Mfr. code

52h

Device code

CODE (03h,04h,06h)

Write command

Address in

Data in

Bus write

[1]

5555h

AAh

Bus write

[2]

2AAAh

55h

Bus write

[3]

5555h

Command code

Bus write

[4]

Address in

Data in

Bus read

Address in

OUT

Command timeout: For each operation the address and data are latched at
bus Write

[4]

and held until the operation completes and times-out. After

time-out the WSM returns the AS29F010 to normal mode. Each individual
operation requires the 4-cycle write command sequence to execute. The
AS29F010 does not remain in command mode after time-out. When a
command times-out only the error flag is not reset.

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Individual write commands are used together in eight program and erase algorithms to guarantee the AS29F010 operating margins for the
life of the part. Refer to the AS29F010 Programming Specification for details on the algorithms for program and erase operation .

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Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.

Mode

IN[3]

Write

[3]

data

IN[4]

Write

[4]

address

IN[4]

data

Read address

Read data

Read delay

Maximum time out

Reset

00h

0000h

Status

100 ns

250 µs

Status

01h

0000h

Status

100 ns

250 µs

ID Read
code

02h

0000h
0001h

x
x

0000h
0001h

Mfr. code

52h

Device code

04h

100 ns
100 ns

250 µs

Verify-0

04h

OUT

25 µs

250 µs

Verify-1

08h

OUT

25 µs

250 µs

Converge

10h

00h

Status

100 ns

250 µs

Program

40h

Status

100 ns

250 µs

Erase

80h

FFh

Status

100 ns

1000 µs

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

4.5

5.0

5.5

Input voltage

2.0

+ 1.0

0.5

0.8

Parameter

Symbol

Min

Max

Unit

Input voltage (Input or DQ pin)

1.0

+ 1.0

Input voltage (A9 pin)

1.0

+13.0

Output voltage

OUT

1.0

+ 1.0

Power supply voltage

+4.5

+5.5

Operating temperature

OPR

+125

°C

Storage temperature (plastic)

STG

+125

°C

Short circuit output current

OUT

100

Latch-up current

±100

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8
8

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0D[LPXP#SRVLWLYH#RYHUVKRRW#ZDYHIRUP

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1RWHV

Not more than one output tested simultaneously. Duration of the short circuit must not be >1 second.

OUT

= 0.5V was selected to avoid test problems

caused by tester ground degradation. (This parameter is sampled and not 100% tested, but guaranteed by characterization.)

The I

current listed includes both the DC operating current and the frequency dependent component (@ 6 MHz). The frequency component typically

is less than 2 mA/MHz with OE at V

active while program or erase operations are in progress.

Parameter

Symbol

Test conditions

Min

Max

Unit

Input load current

= V

to V

, V

= V

MAX

±1

µA

Output leakage current

OUT

= V

to V

, V

= V

MAX

±1

µA

Output short circuit current

OUT

= 0.5V

100

Active current, read @ 6MHz

CE = V

, OE = V

Active current, program/erase

CCPRG

CE = V

, OE = V

Standby current

SB1

(TTL)

CE = V

1.5

SB2

(CMOS) CE = V

1.0

CCPD

RP = 0V

µA

Input: low level

0.5

0.8

Input: high level

2.0

+ 0.3

Output low voltage

= 12mA

0.45

Output high level

OH1

= -2.5 mA

2.4

OH2

= -100 µA

- 0.4

Low V

lock out voltage

LKO

3.2

4.2

Input HV select voltage

11.5

12.5

-2.0V

-0.5V

+0.8V

20 n

+2.0V

+0.5V

+2.0V

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JEDEC
symbol

Std symbol

Parameter

-120

-150

Unit

Min

Max

Min

Max

AVAV

Read cycle time

120

150

AVQV

ACC

Address to output delay

120

150

ELQV

Chip enable to output

120

150

GLQV

Output enable to output

EHQZ

Chip enable to output High Z

GHQZ

Output enable to output High Z

AXQX

Output hold time from addresses, first
occurrence of CE or OE

JEDEC
symbol

Std symbol

Parameter

-120

-150

Unit

Min

Max

Min

Max

AVAV

Write cycle time

120

150

AVWL

Address setup time

WLAX

Address hold time

DVWH

Data setup time

WHDX

Data hold time

OES

Output enable setup time

OEH

Output enable hold time: Read

Output enable hold time:
Toggle and DATA polling

GHWL

Read recover time before write

ELWL

CE setup time

WHEH

CE hold time

WLWH

Write pulse width

WHWL

WPH

Write pulse width high

WHWH1

Programming pulse time

250

µs

WHWH2

Erase pulse time

1000

µs

VCS

setup time

µs

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For all waveforms, A

IN[4:1]

, and D

IN[4:1]

= Address and Data for write cycles 14; D

= Data to be programmed at address A

; Com. = Command byte input

on the DQ pins during Write

[3]

; D

OUT

= Status byte, Manufacturer ID code, or array data for verify.

PWH

ACC

Addresses

Outputs

enabled

valid data out

High Z

stable

WPH

OES

Addresses

Outputs

data in

High-Z

High Z

Addresses

Outputs

[1] = 5555h

[2] = 2AAAh

[3] = 5555h

[4] = A

Write[1]

Write[2]

Write[3]

Write[4]

Read

[1] = AAh

[2] = 55h

[3] = Com.

[4] = D

OUT

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Includes all pins except V

. Test conditions: V

= 5.0V, one pin at a time.

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Parameter

Min

Max

Unit

Input voltage with respect to V

on pin A9

-1.0

+13.5

Input voltage with respect to V

on all DQ pins

-1.0

+1.0

Current

-100

+100

Symbol

Parameter

Test setup

Typical

Max

Unit

Input capacitance

= 0

7.5

OUT

Output capacitance

OUT

= 0

8.5

IN2

Control pin capacitance

= 0

7.5

µF

Symbol

Parameter

Test setup

Typical

Max

Unit

CIN

Input capacitance

= 0

OUT

Output capacitance

OUT

= 0

IN2

Control pin capacitance

= 0

µF

Parameter

Limits

Unit

Min

Typical

Max

Sector erase and Verify-1 time (excludes 00h programming prior to erase)

6.0

8.2

sec

Sector programming time

8.2

sec

Chip programming time

sec

Erase program cycles

10,000

cycles

Byte program time

200

250

µs

Byte verify-0 time

200

250

µs

6.2K

100 pF*

2.7K

Device under test

GND

+5V

*including scope

and jig capacitance

GND

1N3064
or equivalent

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Parameter

Temperature

Min

Unit

Minimum pattern data retention time

150°

years

125°

years

Package \ Access time

120 ns

150 ns

Plastic DIP, 600 mil, 32-pin

AS29F010-120PC

AS29F010-150PC

PLCC, 0.55 × 0.45'' 32-pin

AS29F010-120LC

AS29F010-150LC

TSOP, 8×20 mm, 32-pin

AS29F010-120TC

AS29F010-150TC

AS29F

010

XXX

Flash EEPROM prefix

Device number

Address access time

Package: P = PDIP

L = PLCC
T = TSOP

Commercial temperature range,
0°C to 70 °C

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS29F010-70

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS29F010-70