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· Organization:512K words × 8 bits
· Industrial and commercial temperature
· Sector architecture

- Eight 64K byte sectors
- Erase any combination of sectors or full chip

· Single 5.0±0.5V power supply for read/write operations
· Sector protection
· High speed 55/70/90/120/150 ns address access time
· Automated on-chip programming algorithm

- Automatically programs/verifies data at specified

address

· Automated on-chip erase algorithm

- Automatically preprograms/erases chip or specified

sectors

· 10,000 write/erase cycle endurance
· Low power consumption

- 30 mA maximum read current
- 60 mA maximum program current
- 400 µA typical standby current

· JEDEC standard software, packages and pinouts

- 32-pin TSOP
- 32-pin PLCC

· Detection of program/erase cycle completion

- DQ7 DATA polling
- DQ6 toggle bit

· Erase suspend/resume

- Supports reading data from or programming data to

a sector not being erased

· Low V

write lock-out below 2.8V

/RJLF#EORFN#GLDJUDP

X decoder

Cell matr

Y decoder

Y gating

Data latch

Chip enable

r
ess l

a
tc

Input/output

buffers

Sector protect

Command

Program/erase

control

detector

Erase voltage

generator

Program voltage

generator

Timer

A0A18

STB

Output enable

Logic

DQ0DQ7

switches

3LQ#DUUDQJHPHQW

A17

A14

A13

A11

A10
CE

DQ7

DQ6

DQ5

A18

A16

A15

A12

A5
A4

DQ0

DQ1

DQ2

DQ4

DQ3

8
9

10
11
12

32
31

22
21

32-pin TSOP

32-pin PLCC

DQ0

DQ4

DQ6

DQ1

DQ2

DQ3

DQ5

A14

A13

A11

A10

DQ7

A16

A17

A12

A15

A18

AS29F040

6HOHFWLRQ#JXLGH

AS29F040-55

AS29F040-70

AS29F040-90

AS29F040-120 AS29F040-150 Unit

Maximum access time

120

150

Maximum chip enable access time

120

150

Maximum output enable access time

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The AS29F040 is a 4-megabit, 5-volt-only Flash memory device organized as 512K bytes of 8 bits each. For flexible erase an
program capability, the 4 megabits of data is divided into eight 64K-byte sectors. The ×8 data appears on DQ0DQ7. The
AS29F040 is offered in JEDEC standard 32-pin TSOP and 32-pin PLCC packages. This device is designed to be programmed an
erased in-system with a single 5.0V V

supply. The device can also be reprogrammed in standard EPROM programmers.

The AS29F040 offers access times of 55/70/90/120/150 ns, allowing 0-wait state operation of high-speed microprocessors. To
eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls

The AS29F040 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command register
use standard microprocessor write timings. An internal state machine uses register contents to control the erase and programming
circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data
operates from the device in the same manner as other Flash or EPROM devices. The program command sequence is used to invoke
the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin.
The erase command sequence is used to invoke the automated on-chip erase algorithm that preprograms the sector if it is not
already programmed before executing the erase operation, times the erase pulse widths, and verifies proper cell margin.

Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors.
A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase operations in
any or all combinations of the eight sectors. The device provides true background erase with Erase Suspend, which puts erase
operations on hold to either read data from or program data to a sector that is not being erased. The chip erase command will
automatically erase all unprotected sectors.

A factory shipped AS29F040 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the
array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase
returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors.

The device features single 5.0V power supply operation for read, write, and erase functions. Internally generated and regulate
voltages are provided for the program and erase operations. A low V

detector automatically inhibits write operations during

power transtitions. DATA polling of DQ7 or toggle bit (DQ6) may be used to detect end-of-program or erase operations. The
device automatically resets to read mode after program and/or erase operations are completed.

The AS29F040 resists accidental erasure or spurious programming signals resulting from power transitions. Control register
architecture permits the alteration of memory contents only after successful completion of specific command sequences. During
power up, the device is set to read mode with all program and/or erase commands disabled when V

is less than V

LKO

(lockout

voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. CE and WE must be logical
zero and OE a logical one to initiate write commands.

The AS29F040 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are programme
one at a time using the EPROM programming mechanism of hot electron injection.

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L = Low (<V

); H = High (>V

); V

= 12.0 ± 0.5V; X = don't car .

0RGH#GHILQLWLRQV

Mode

DQ0-DQ7

ID read MFR code

Code

ID read device code

Code

Read

OUT

Standby

High Z

Output disable

High Z

Write

Enable sector protect

Pulse/L

Sector unprotect

Pulse/L

Verify sector protect

Code

Item

Description

ID MFR code,
device code

Selected by A9 = V

(11.512.5V), CE = OE = A1 = A6 = L, enabling outputs.

When A0 is low (V

) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.

When A0 is high (V

), D

OUT

represents the device code for the AS29F040.

Read mode

Selected with CE = OE = L, WE = H. Data is valid in t

ACC

time after addresses are stable, t

after CE is low

and t

after OE is low.

Standby

Selected with CE = H. Part is powered down, and I

reduced to <1.0 mA for TTL input levels and <100 µA

for CMOS levels. If activated during an automated on-chip algorithm, the device completes the operation
before entering standby.

Output disable Part remains powered up; but outputs disabled with OE pulled high.

Write

Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command
register. Contents of command register serve as inputs to the internal state machine. Address latching occurs
on the falling edge of WE or CE, whichever occurs late . Data latching occurs on the rising edge WE or CE,
whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.

Enable
sector protect

Hardware protection circuitry implemented with external programming equipment causes the device to
disable program and erase operations for specified sectors.

Sector
unprotect

Disables sector protection for all sectors using external programming equipment. All sectors must be
protected prior to sector unprotection.

Verify
sector protect

Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
programming equipment. Determine if sector protection exists in a system by writing the ID read command
sequence and reading location XXX02h, where address bits A1618 select the defined sector addresses.
A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.

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L = Low (<V

); H = High (>V

); X = Don't care.

&RPPDQG#IRUPDW

Bus operations defined in "Mode definitions," on page 3.

Reading from or programming to non-erasing sectors allowed in Erase Suspend mode.

Address bit A15 = X = Don't care for all address commands except Program Address.

Address bit A16 = X = Don't care for all address commands except Program Address and Sector Address.

Address bit A17 = X = Don't care for all address commands except Program Address and Sector Address.

Address bit A18 = X = Don't care for all address commands except Program Address and Sector Address.

Sector

Equal sector architecture

ID sector address

Addresses

Size (Kbytes)

A18

A17

A16

00000h0FFFFh

10000h1FFFFh

20000h2FFFFh

30000h3FFFFh

40000h4FFFFh

50000h5FFFFh

60000h6FFFFh

70000h7FFFFh

Mode

A18A16

A8A7

A5A2

Code on DQ0DQ7

MFG code (Alliance
Semiconductor)

52h

Device code

A4h

Sector protection

Sector
address

01h protected
00h unprotected

Command
sequence

Required

bus cycles

1st bus write

cycle

2nd bus write

cycle

3rd bus write

cycle

4th bus read/write

cycle

5th bus write

cycle

6th bus write

cycle

Address

Data

Address

Data

Address

Data

Address

Data

Address

Data

Address

Data

Reset/read

XXXXh

F0h

Read

Address

Read

Data

Reset/read

5555h

AAh

2AAAh

55h

5555h

F0h

Read

Address

Read

Data

Autoselect ID
read

5555h

AAh

2AAAh

55h

5555h

90h

00h

MFR code

52h

01h

Device code

A4h

XXX02h

Sector

protection

01 = protected

00 = unprotected

Program

5555h

AAh

2AAAh

55h

5555h

A0h

Program

Address

Program

Data

Chip erase

5555h

AAh

2AAAh

55h

5555h

80h

5555h

AAh

2AAAh

55h

5555h

10h

Sector erase

5555h

AAh

2AAAh

55h

5555h

80h

5555h

AAh

2AAAh

55h

Sector

Address

30h

Sector erase
suspend

XXXXh

B0h

Sector erase
resume

XXXXh

30h

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Item

Description

Reset/read

Initiate read or reset operations by writing the read/reset command sequence into the command
register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode
until command register contents are altered.

Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no
spurious memory content alterations during power up.

ID read

AS29F040 provides manufacturer and device codes in two ways. External PROM programmers typically
access the device codes by driving +12V on A9. AS29F040 also contains an ID read command to read
the device code with only +5V, since multiplexing +12V on address lines is generally undesirable.

Initiate device ID read by writing the ID read command sequence into the command register. Follow
with a read sequence from address XXX00h to return MFG code. Follow ID read command sequence
with a read sequence from address XXX01h to return device code.

To verify write protect status on sectors, read address XXX02h. Sector addresses A18A16 produc e a1
on DQ0 for protected sector and a 0 for unprotected sector.

Exit from ID read mode with Read/Reset command sequence.

Byte/word
programming

Programming the AS29F040 is a four bus cycle operation performed on a byte-by-byte basis. Two
unlock write cycles precede the program setup command and program data write cycle. Upon
execution of the program command, no additional CPU controls or timings are necessary. Addresses are
latched on the falling edge of CE or WE, whichever is last; data is latched on the rising edge of CE or
WE, whichever is first. The AS29F040's automated on-chip program algorithm provides adequate
internally-generated programming pulses and verifies the programmed cell margin.

Check programming status by sampling data on the DATA polling (DQ7), or toggle bit (DQ6). The
AS29F040 returns the equivalent data that was written to it (as opposed to complemented data), to
complete the programming operation.

The AS29F040 ignores commands written during the programming operation.

AS29F040 allows programming in any sequence, across any sector boundary. Changing data from 0 to 1
requires an erase operation. Attempting to program data 0 to 1 results in DQ5 = 1 (exceeded
programming time limits); reading this data after a read/reset operation returns a 0. When
programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state , areset
command returns the device to read mode.

Chip erase

Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock
write cycles; and finally the Chip erase command.

Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase
algorithm is invoked with the Chip erase command sequence, AS29F040 automatically programs and
verifies the entire memory array for an all-zero pattern prior to erase. The AS29F040 returns to read
mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS29F040-150LI

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS29F040-150LI