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· Organization: 256K×8 or 128K×16
· Sector architecture

- One 16K; two 8K; one 32K; and three 64K byte sectors
- Boot code sector architecture--T (top) or B (bottom)
- Erase any combination of sectors or full chip

· Single 5.0±0.5V power supply for read/write operations
· Sector protection
· High speed 55/70/90/120 ns address access time
· Automated on-chip programming algorithm

- Automatically programs/verifies data at specified ad-

dress

· Automated on-chip erase algorith

- Automatically preprograms/erases chip or specified sec-

tors

· 10,000 write/erase cycle endurance
· Hardware RESET pin

- Resets internal state machine to read mode

· Low power consumption

- 20 mA typical read current
- 30 mA typical program current
- 300 µA typical standby current
- 1 µA typical standby current (RESET = 0)

· JEDEC standard software, packages and pinouts

- 48-pin TSOP
- 44-pin SO

· Detection of program/erase cycle completion

- DQ7 DATA polling
- DQ6 toggle bit
- RY/BY output

· Erase suspend/resume

- Supports reading data from a sector not being erased

· Low V

write lock-out below 2.8V

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X decoder

Cell matrix

Y decoder

Y gating

Data latch

Chip enable

s
la

t
c
h

Input/output

buffers

Sector protect

Command

Program/erase

control

detector

Erase voltage

generator

Program voltage

generator

Timer

A0A16

STB

Output enable

Logic

RY/BY

BYTE

RESET

DQ0DQ15

switches

A-1

3LQ#DUUDQJHPHQW

A14

A15

A16

BYTE

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

44-pin SO

DQ3

DQ11

A10

A11

A12

A13

RY/BY

RESET

A1
0

A1
1

A1
2

A1
3

A1
4

A1
5

A1
6

BY
T

DQ
1

/A-

DQ
7

DQ
1

RE
S
E

RY
/

DQ
2

DQ
1

DQ
3

DQ
1

DQ
4

DQ
1

DQ
5

DQ
6

DQ
1

48-pin TSOP

DQ
0

DQ
8

DQ
1

DQ
9

AS29F200

AS29

200

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29F200-55

29F200-70

29F200-90

29F200-120 Unit

Maximum access time

120

Maximum chip enable access time

120

Maximum output enable access time

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The AS29F200 is a 2 megabit, 5 volt only Flash memory organized as 256K bytes of 8 bits each or 128K words of 16 bits each. For flexible
erase and program capability, the 2 megabits of data is divided into 7 sectors: one 16K byte, two 8K byte, one 32K byte, and three 64K bytes.
The ×8 data appears on DQ0DQ7; the ×16 data appears on DQ0DQ15. The AS29F200 is offered in JEDEC standard 44-pin SO and 48-pin
TSOP packages. This device is designed to be programmed and erased in-system with a single 5.0V V

supply. The device can also be

reprogrammed in standard EPROM programmers.

The AS29F200 offers access times of 55/70/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate bus
contention the device has separate chip enable ( CE), write enable ( WE), and output enable ( OE) controls. Word mode (×16 output) is
selected by BYTE = High.

The AS29F200 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command register using
standard microprocessor write timings. An internal state-machine uses register contents to control the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data from the device in the same
manner as other Flash or EPROM devices. Use the program command sequence to invoke the automated on-chip programming algorithm
that automatically times the program pulse widths and verifies proper cell margin. Use the erase command sequence to invoke the automated
on-chip erase algorithm that preprograms the sector if it is not already programmed before executing the erase operation, times the erase
pulse widths, and verifies proper cell margin.

Boot sector architecture enables the device to boot from either the top (AS29F200T) or bottom (AS29F200B) sector. Sector erase architecture
allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically eras es and
verifies within 1.6 seconds. Hardware sector protection disables both program and erase operations in all or any combination of the seven
sectors. The device provides background erase with Erase Suspend, which puts erase operations on hold to read data from a sector that is not
being erased. The chip erase command will automatically erase all unprotected sectors.

A factory shipped AS29F200 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one
byte/word at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes/
words in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors.

The device features single 5.0V power supply operation for both read and write functions. Internally generated and regulated voltages are
provided for the program and erase operations. A low V

detector automatically inhibits write operations during power transtitions. The

RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of program or erase operations. The device automatically
resets to the read mode after program/erase operations are completed.

The AS29F200 resists accidental erasure or spurious programming signals resulting from power transitions. Control register archi tecture
permits alteration of memory contents only after successful completion of specific command sequences. During power up, the device is set
to read mode with all program/erase commands disabled when V

is less than V

LKO

(lockout voltage). The command registers are not

affected by noise pulses of less than 5 ns on OE, CE, or WE. CE and WE must be logical zero and OE a logical one to initiate write commands.

When the device's hardware RESET pin is driven low, any program/erase operation in progress will be terminated and the internal state
machine will be reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an automated on-
chip program/erase algorithm, data in address locations being operated on will become corrupted and require rewriting. Resetting the
device enables the system's microprocessor to read boot-up firmware from the Flash memory.

The AS29F200 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes/words are programmed
one at a time using EPROM programming mechanism of hot electron injection.

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In word mode, there are one 8K word, two 4K word, one 16K word, and three 32K word sectors. Address range is A16A-1 if BYTE = V

; address range is

A16A0 if BYTE = V

,'#6HFWRU#DGGUHVV#WDEOH

2SHUDWLQJ#PRGHV

L = Low (<V

); H = High (>V

); V

= 12.0 ± 0.5V; X = don't care; In ×16 mode, BYTE = V

. In ×8 mode, BYTE = V

and DQ814 is High Z with

DQ15 = A-1(X).

Sector

Bottom boot sector architecture (AS29F200B)

Top boot sector architecture (AS29F200T)

×8

×16

Size

(Kbytes)

×8

×16

Size

(Kbytes)

00000h03FFFh

00000h01FFFh

00000h0FFFFh

00000h07FFFh

04000h05FFFh

02000h02FFFh

10000h1FFFFh

08000h0FFFFh

06000h07FFFh

03000h03FFFh

20000h2FFFFh

10000h17FFFh

08000h0FFFFh

04000h07FFFh

30000h37FFFh

18000h1BFFFh

10000h1FFFFh

08000h0FFFFh

38000h39FFFh

1C000h1CFFFh

20000h2FFFFh

10000h17FFFh

3A000h3BFFFh

1D000h1DFFFh

30000h3FFFFh

18000h1FFFFh

3C000h3FFFFh

1E000h1FFFFh

Sector

Bottom boot sector address (AS29F200B)

Top boot sector address (AS29F200T)

A16

A15

A14

A13

A12

A16

A15

A14

A13

A12

Mode

RESET

ID read MFR code

Code

ID read device code

Code

Read

OUT

Standby

High Z

Output disable

High Z

Write

Enable sector protect

Pulse/L

Sector unprotect

Pulse/L

Verify sector protect

Code

Temporary sector
unprotect

Hardware Reset

High Z

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Key: L =Low (<V

); H = High (>V

); X =Don't care; T = top; B = botto

Item

Description

ID MFR code,
device code

Selected by A9 = V

(11.512.5V), CE = OE = A1 = A6 = L, enabling outputs.

When A0 is low (V

) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.

When A0 is high (V

), D

OUT

represents the device code for the AS29F200.

Read mode

Selected with CE = OE = L, WE = H. Data is valid in t

ACC

time after addresses are stable, t

after CE is low

and t

after OE is low.

Standby

Selected with CE = H. Part is powered down, and I

reduced to <2.0 mA for TTL input levels. If activated

during an automated on-chip algorithm, the device completes the operation before entering standby.

Output disable Part remains powered up; but outputs disabled with OE pulled high.

Write

Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command
register. Contents of command register serve as inputs to the internal state machine. Address latching occurs
on the falling edge of WE or CE, whichever occurs late . Data latching occurs on the rising edge WE or CE,
whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.

Enable
sector protect

Hardware protection circuitry implemented with external programming equipment causes the device to
disable program and erase operations for specified sectors.

Sector
unprotect

Disables sector protection for all sectors using external programming equipment. All sectors must be
protected prior to sector unprotection.

Verify
sector protect

Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
programming equipment. Determine if sector protection exists in a system by writing the ID read command
sequence and reading location XXX02h, where address bits A1216 select the defined sector addresses. A
logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.

Temporary
sector
unprotect

Temporarily disables sector protection for in-system data changes to protected sectors. Apply +12V to RESET
to activate sector unprotect mode. During temporary sector unprotect mode, program protected sectors by
selecting the appropriate sector address. All protected sectors revert to protected state on removal of +12V
from RESET.

RESET

Resets the write and erase state machine to read mode. If device is programming or erasing when
RESET = L, data may be corrupted.

Deep
power down

Hold RESET low to enter deep power down mode (

10 µA CMOS). Recovery time to active mode is 1.5 µs.

Mode

A16A12

Code

MFR code (Alliance Semiconductor)

52h

Device code

×8 T boot

51h

×8 B boot

57h

×16 T boot

2251h

×16 B boot

2257h

Sector protection

Sector address

01h protected
00h unprotected

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Toggles with OE or CE only for erasing or erase suspended sector addresses.

Toggles only if DQ5 = 1 and address applied is within sector that exceeded timing limits.

DQ8DQ15 = Don't care in ×16 mode.

&RPPDQG#GHILQLWLRQV

Status

DQ7

DQ6

DQ5

DQ3

DQ2

RY/BY

In progress

Auto programming (byte/word)

DQ7

Toggle

No toggle

Program/erase in auto erase

Toggle

Erase
suspend
mode

Read erasing sector

No toggle

Toggle

Read non-erasing
sector

Data

Program in erase
suspend

DQ7

Toggle

Exceeded time limits

Auto programming (byte/word)

DQ7

Toggle

No toggle

Program/erase in auto erase

Toggle

Program in erase suspend

DQ7

Toggle

No toggle

Item

Description

Reset/Read

Initiate read or reset operations by writing the Read/Reset command sequence into the command
register. This allows the microprocessor to retrieve data from the memory. Device remains in read
mode until command register contents are altered.

Device automatically powers up in read/reset state. This feature allows only reads, therefore
ensuring no spurious memory content alterations during power up.

ID Read

AS29F200 provides manufacturer and device codes in two ways. External PROM programmers
typically access the device codes by driving +12V on A9. AS29F200 also contains an ID read
command to read the device code with only +5V, since multiplexing +12V on address lines is
generally undesirable.

Initiate device ID read by writing the ID Read command sequence into the command register.
Follow with a read sequence from address XX00h to return MFG code. Follow ID read command
sequence with a read sequence from address XX01h to return device code.

To verify write protect status on sectors, read address XX02h. Sector addresses A16A12 produce a
1 on DQ0 for protected sector and a 0 for unprotected sector.

Exit from ID read mode with Read/Reset command sequence.

Hardware Reset

Holding RESET low for 500 ns resets the device, terminating any operation in progress; data
handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is driven
low. RY/BY remains low until the RESET operation is completed. After RESET is set high, there is a
delay of 1.5 µs for the device to permit read operations.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS29F200B-90SI

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS29F200B-90SI