Document Outline
- 1 OP= operation code. A0~A11 see page 5.
- 2 MRS can be issued only when both banks are precharged and no data burst is ongoing. A new comma...
- 3 Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic. Auto/sel...
- 4 A11: bank select address. If low during read, write, row active and precharge, bank A is select...
- 5 A new read/write/deac command to the same bank cannot be issued during a burst read/write with ...
- 6 Burst stop command valid at every burst length except full-page burst.
- 7 DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0...
- 1 IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum ...
- 2 Other input signals are allowed to transition no more than once in any two-clock period and are...
- 3 Address transitions average one transition every two-clock period.
- 4 The IDD current will decrease as the CAS-latency is reduced. This is due to the fact that the m...
- 5 tCK = 7 ns for 7, 8 ns for 8, and 10 ns for 10.
- 6 If clock tr > 1 ns, (tr/2 0.5)ns should be added to the parameter.
- 7 If clock (tr and tf) > 1 ns, [(tr + tf)/2 1] ns should be added to the parameter.
- 8 VIH overshoot: VIH(max) = VDDQ + 2V for a pulse width 3 ns, and the pulse width cannot be gre...
- 9 Required clocks are specified by JEDEC functionalisty and are not dependent on any timing param...
- 10 The clock frequency must remain constant during access or precharge states (READ, WRITE, inclu...
- 11 Timing actually specified tWR plus tRP; clock(s) specified as a reference only at minimum cycl...
- 12 Timing actually specified by tWR.
- 13 tHZ defines the time at which the output achieves the open circuit condition; it is not a refe...
- 14 CLK must be toggled a minimum of two times during this period.
- 15 Enables on-chip refresh and address counters.
- 16 All voltages referenced to VSS.
- 17 The minimum specifications are used only to indicate the cycle time at which proper operation ...
- 18 A proper power-up initialization sequence (as described on page10) is needed before proper de...
- 19 AC characteristics assume tT = 1 ns.
- 20 In addition to meeting the transition rate specification, the clock and CKE must transit betwe...
- 21 AC timing and IDD tests have VIL = 0V and VIH = 3.0 V with timing referenced to 1.4V crossover...
- 22 IDD specifications are tested after the device is properly initialized.
- 23 Minimum clock cycles = (minimum time/clock cycle time) rounded up.
- 1 Apply power, start clock, and assert CKE and DQM high. All other signals are NOP.
- 2 After power-up, pause for a minimum of 200s. CKE/DQM = high; all others NOP.
- 3 Precharge both banks.
- 4 Perform Mode Register Set command to initialize mode register.
- 5 Perform a minimum of 8 auto refresh cycles to stabilize internal circuitry.
May 2001
Copyright Alliance Semiconductor. All rights reserved.
AS4LC2M8S1
AS4LC2M8S0
AS4LC1M16S1
AS4LC1M16S0
3.3V 2M
8/1M
16 CMOS synchronous DRAM
5/21/01; v.1.1
Alliance Semiconductor
P. 1 of 29
Preliminary
Auto refresh and self refresh
PC100 functionality
Automatic and direct precharge including concurrent
autoprecharge
Burst read, write/Single write
Random column address assertion in every cycle, pipelined
operation
LVTTL compatible I/O
3.3V power supply
JEDEC standard package, pinout and function
- 400 mil, 44-pin TSOP 2 (2M 8)
- 400 mil, 50-pin TSOP 2 (1M 16)
Read/write data masking
Programmable burst length (1/2/4/8/ full page)
Programmable burst sequence (sequential/interleaved)
Programmable CAS latency (1/2/3)
Selection guide
Symbol
7
8
10
Unit
Bus frequency (CL = 3)
f
Max
143
125
100
MHz
Maximum clock access time (CL = 3)
t
AC
5.5
6
6
ns
Minimum input setup time
t
S
2
2
2
ns
Minimum input hold time
t
H
1.0
1.0
1.0
ns
Row cycle time (CL = 3, BL = 1)
t
RC
70
80
80
ns
Maximum operating current ([
16], RD or
WR, CL = 3), BL = 2
I
CC1
130
100
100
mA
Maximum CMOS standby current, self refresh
I
CC6
1
1
1
mA
Pin designation
Pin(s)
Description
DQM (2M 8)
UDQM/LDQM (1M 16)
Output disable/write mask
A0 to A10
Address inputs
RA0 10
CA0 7 (
16)
CA0 8 (
8)
A11
Bank address (BA)
DQ0 to DQ7 (2M
8)
DQ0 to DQ15 (1M
16)
Input/output
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
CS
Chip select
V
CC
, V
CCQ
Power (3.3V 0.3V)
V
SS
, V
SSQ
Ground
CLK
Clock input
CKE
Clock enable
Pin arrangement
V
CC
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
CCQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
CCQ
LDQM
WE
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
CCQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
CCQ
NC
UDQM
CLK
CKE
NC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
TSOP 2
AS4LC1M16S
0
23
24
25
28
27
26
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
V
SSQ
DQ1
V
CCQ
DQ2
V
SSQ
DQ3
V
CCQ
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
V
SS
DQ7
V
SSQ
DQ6
V
CCQ
DQ5
V
SSQ
DQ4
V
CCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
TSOP 2
AS4LC2
M8S0
AS
4LC2M8S1
and
and
AS4LC1M16S
1
Features
Organization
- 1,048,576 words 8 bits 2 banks (2M 8)
11 row, 9 column address
- 524,288 words 16 bits 2 banks (1M 16)
11 row, 8 column address
All signals referenced to positive edge of clock, fully
synchronous
Dual internal banks controlled by A11 (bank select)
High speed
- 143/125/100 MHz
- 7/8/10 ns clock access time
Low power consumption
- Active:
576 mW max
- Standby: 7.2 mW max, CMOS I/O
2048 refresh cycles, 32 ms refresh interval
4096 refresh cycles, 64 ms refresh interval
LEGEND
2M
8
1M
16
Configuration
1M
8 2 banks
512K
16 2 banks
Refresh Count
2K/4K
2K/4K
Row Address
(A0 A10)
(A0 A10)
Bank Address
2 (BA)
2 (BA)
Column Address
512 (A0 A8)
256 (A0 A7)
5/21/01; v.1.1
Alliance Semiconductor
P. 2 of 29
AS4LC2M8S1
AS4LC1M16S1
Functional description
The AS4LC2M8S1, AS4LC2M8S0, and AS4LC1M16S1, AS4LC1M16S0 are high-performance 16-megabit CMOS Synchronous Dynamic
Random Access Memory (SDRAM) devices organized as 1,048,576 words 8 bits 2 banks (2048 rows 512 columns) and 524,288
words 16 bits 2 banks (2048 rows 256 columns), respectively. Very high bandwidth is achieved using a pipelined architecture where
all inputs and outputs are referenced to the rising edge of a common clock. Programmable burst mode can be used to read up to a full page
of data (512 bytes for 2M 8 and 256 bytes for 1M 16) without selecting a new column address.
The operational advantages of an SDRAM are as follows: (1) the ability to synchronously output data at a high clock frequency with
automatic increments of column-address (burst access); (2) bank-interleaving, which hides precharge time and attains seamless operation;
and (3) the capability to change column-address randomly on every clock cycle during burst access.
This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type
(sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum
frequency of operation. This feature enables flexible performance optimization for a variety of applications.
SDRAM commands and functions are decoded from control inputs. Basic commands are as follows:
Both devices are available in 400-mil plastic TSOP type 2 package. The AS4LC2M8S1/ AS4LC2M8S0 have 44 pins, and the AS4LC1M16S1/
AS4LC1M16S0 have 50 pins. All devices operate with a power supply of 3.3V 0.3V. Multiple power and ground pins are provided for low
switching noise and EMI. Inputs and outputs are LVTTL compatible.
Logic block diagram
For AS4LC2M8S1/AS4LC2M8S0, Banks A and B will read 1M 8 (2048 512 8).
Mode register set
Deactivate bank
Deactivate all banks
Select row; activate bank
Select column; write
Select column; read
Deselect; power down
CBR refresh
Auto precharge with read/write
Self-refresh
RAS
CAS
WE
CLK
CKE
Clock generator
Mode register
Com
m
an
d de
c
o
der
Con
t
r
o
l
log
i
c
Row
address
buffer
Refresh
counter
Column
address
buffer
Burst
counter
Ro
w de
code
r
Sense amplifier
Column decoder and
latch circuit
Data control circuit
La
tc
h
cir
c
uit
In
pu
t a
n
d ou
tpu
t
b
u
f
f
e
r
DQ
DQMU/DQML
CS
Bank select
A11
Bank B
Bank A
512K
16 (2048 256 16)
512K
16 (2048 256 16)
A[10:0]
AS4LC2M8S1
AS4LC1M16S1
5/21/01; v.1.1
Alliance Semiconductor
P. 3 of 29
Pin descriptions
Pin
Name
Description
CLK
System clock
All operations synchronized to rising edge of CLK.
CKE
Clock enable
Controls CLK input. If CKE is high, the next CLK rising edge is valid.
If CKE is low, the internal clock is suspended from the next clock
cycle and the burst address and output states are frozen. If both banks
are idle and CKE goes low, the SDRAM will enter power down mode
from the next clock cycle. When in power down mode and CKE is
low, no input commands will be acknowledged. To exit power down
mode, raise CKE high before the rising edge of CLK.
CS
Chip select
Enables or disables device operation by masking or enabling all inputs
except CLK, CKE, UDQM/LDQM (16), DQM (8).
A0~A10
Address
Row and column addresses are multiplexed. Row address: A0~A10.
Column address (2M 8): A0~A8. Column address (1M 16):
A0~A7.
A11
Bank select
Memory cell array is organized in 2 banks. A11 selects which internal
bank will be active. A11 is latched during bank activate, read, write,
mode register set, and precharge operations. Asserting A11 low
selects Bank A; A11 high selects Bank B.
RAS
CAS
WE
Row address strobe
Column address strobe
Write enable
Command inputs.
RAS, CAS, and WE, along with CS, define the command being
entered.
8: DQM
16: UDQM, LDQM
Output disable/ write mask
Controls I/O buffers. When DQM is high, output buffers are disabled
during a read operation and input data is masked during a write
operation. DQM latency is 2 clocks for Read and 0 clocks for Write.
For 16, LDQM controls the lower byte (DQ0 7) and UDQM
controls the upper byte (DQ8 15). UDQM and LDQM are
considered to be in the same state when referred to jointly as DQM.
DQ0~DQ15
Data input/output
Data inputs/outputs are multiplexed.
V
CC
/V
SS
Power supply/ground
Power and ground for core logic and input buffers.
V
CCQ
/V
SSQ
Data output power/ground
Power and ground for data output buffers.
5/21/01; v.1.1
Alliance Semiconductor
P. 4 of 29
AS4LC2M8S1
AS4LC1M16S1
Operating modes
1
OP= operation code.
A0~A11 see page 5.
2
MRS can be issued only when both banks are precharged and no data burst is ongoing. A new command can be issued 2 clock cycles after MRS.
3
Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic.
Auto/self refresh can only be issued after both banks are precharged.
4
A11: bank select address. If low during read, write, row active and precharge, bank A is selected.
If high during those states, bank B is selected. Both banks are selected and A11 is ignored if A10 is high during row precharge.
5
A new read/write/deac command to the same bank cannot be issued during a burst read/write with auto precharge.
A new row active command can be issued after t
RP
from the end of the burst.
6
Burst stop command valid at every burst length except full-page burst.
7
DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0).
Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2).
Command
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM
A11
A10
A9A0
Note
Mode register set
H
X
L
L
L
L
X
Op code
1,2
Auto refresh
H
H
L
L
L
H
X
X
3
Self
refresh
Entry
H
L
L
L
L
H
X
X
3
Exit
L
H
L
H
H
H
X
X
3
H
X
X
X
X
X
3
Bank activate
H
X
L
L
H
H
X
V
*
* V = Valid.
row address
Read
Auto precharge disable
H
X
L
H
L
H
X
V
L
column
address
4
Auto precharge enable
H
4,5
Write
Auto precharge disable
H
X
L
H
L
L
X
V
L
column
address
4
Auto precharge enable
H
4,5
Burst stop
H
X
L
H
H
L
X
X
6
Precharge
Selected bank
H
X
L
L
H
L
X
V
L
X
Both banks
X
H
Clock suspend or
active power down
Entry
H
L
H
X
X
X
X
X
L
V
V
V
X
Exit
L
H
X
X
X
X
X
Precharge power
down mode
Entry
H
L
H
X
X
X
X
X
L
H
H
H
X
Exit
L
H
H
X
X
X
X
L
H
H
H
X
DQM
H
X
X
X
X
X
V
X
X
X
7
No operation command
H
X
H
X
X
X
X
X
L
H
H
H
X
AS4LC2M8S1
AS4LC1M16S1
5/21/01; v.1.1
Alliance Semiconductor
P. 5 of 29
Mode register fields
RFU = 0 during MRS cycle.
Burst sequence (burst length = 4)
Burst sequence (burst length = 8)
Register programmed with MRS
Address
A11~A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
RFU
WBL
TM
CAS
latency
BT
Burst length
Write burst length
Burst type
A9
Length
A3
Type
0
Programmed
burst length
0
Sequential
1
Interleaved
1
Single burst
Test mode
A8
A7
Type
0
0
Mode register set
0
1
Reserved
1
0
Reserved
1
1
Reserved
CAS latency
Burst length
A6
A5
A4
Latency
A2
A1
A0
BT = 0
BT = 1
0
0
0
Reserved
0
0
0
1
1
0
0
1
1
0
0
1
2
2
0
1
0
2
0
1
0
4
4
0
1
1
3
0
1
1
8
8
1
X
X
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full page
Reserved
Initial address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
Initial address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
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