ALLIANCE
SEMICONDUCTOR
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128
128K
K
8
8
C
CM
MO
OS
S SSR
RA
AM
M
A
ASS7
7C
C1024
1024
A
ASS7
7C
C31024
31024
12
128
8KK
8
8 C
CM
MO
OS
S SSRRA
AM
M
DID 11-20000-*A. 5/29/97
Copyright 1997 Alliance Semiconductor. All rights reserved.
Features
Organization: 131,072 words 8 bits
High speed
- 10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
Low power consumption
- Active: 660 mW max (15 ns cycle)
- Standby: 55 mW max, CMOS I/O
- Very low DC component in active power
2.0V data retention
Equal access and cycle times
Easy memory expansion with CE1, CE2, OE inputs
TTL/LVTTL-compatible, three-state I/O
32-pin JEDEC standard packages
- 300 mil PDIP and SOJ
Socket compatible with 7C512 (64K8)
- 400 mil PDIP and SOJ
- 820 TSOP
ESD protection
2000 volts
Latch-up current
200 mA
3.3V and 5.0V versions available
Industrial and commercial temperature available
Logic block diagram
512
256
8
Array
(1,048,576)
Se
n
s
e
a
m
p
Input buffer
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
A1
6
I/O0
I/O7
OE
CE1
WE
Column decoder
R
o
w d
eco
d
e
r
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
Vcc
GND
A8
CE2
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
A
S7C
10
24
DIP, SOJ
Vcc
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
TSOP 820
I/O2
GND
I/O4
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
AS7C1024
20
19
15
16
18
17
Selection guide
Shaded areas contain advance information.
7C1024-10
7C1024-12
7C31024-12
7C1024-15
7C31024-15
7C1024-20
7C31024-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
3
3
4
5
ns
Maximum operating current
AS7C1024
175
160
120
110
mA
AS7C31024
100
70
65
mA
Maximum CMOS standby current
10.0
10.0
10.0
10.0
mA
AS7C1024
AS7C31024
2
DID F11-20000-*A. 5/29/97
Copyright 1997 Alliance Semiconductor. All rights reserved.
Functional description
The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memories (SRAM) organized as 131,072
words 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 3/3/4/5 ns are ideal for
high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory
systems.
When CE1 is HIGH or CE2 is LOW the device enters standby mode. The standard AS7C1024 is guaranteed not to exceed 55 mW power
consumption in standby mode. Both devices offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written
on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL/LVTTL-compatible, and operation is from a single 5V supply (AS7C1024) or 3.3V supply (AS7C31024).
The AS7C1024 and AS7C31024 are packaged in common industry standard packages.
Absolute maximum ratings
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don't Care, L = LOW, H = HIGH
Recommended operating conditions
V
IL
min = 3.0V for pulse width less than t
RC
/2.
Parameter
Symbol
Min
Max
Unit
Voltage on any pin relative to GND
V
t
0.5
+7.0
V
Power dissipation
P
D
1.0
W
Storage temperature (plastic)
T
stg
55
+150
o
C
Temperature under bias
T
bias
10 +85
o
C
DC output current
I
out
20
mA
CE1
CE2
WE
OE
Data
Mode
H
X
X
X
High Z
Standby (I
SB
, I
SB1
)
X
L
X
X
High Z
Standby (I
SB
, I
SB1
)
L
H
H
H
High Z
Output disable
L
H
H
L
D
out
Read
L
H
L
X
D
in
Write
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage
AS7C1024
V
CC
4.5
5.0
5.5
V
AS7C31024
V
CC
3.0
3.3
3.6
V
GND
0.0
0.0
0.0
V
Input voltage
AS7C1024
V
IH
2.2
V
CC
+ 0.5
V
AS7C31024
V
IH
2.0
V
CC
+ 0.5
V
V
IL
0.5
0.8
V
AS7C1024
AS7C31024
3
DID F11-20000-*A. 5/29/97
Copyright 1997 Alliance Semiconductor. All rights reserved.
DC operating characteristics
1
Shaded areas contain advance information.
Capacitance
2
(f = 1 MHz, T
a
= Room temperature, V
CC
= 5V)
Read cycle
3,9,12
Parameter
Symbol
Test conditions
-10
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Input leakage
current
|
I
LI
|
V
CC
= Max,
V
in
= GND to V
CC
1
1
1
1
A
Output leakage
current
|
I
LO
|
CE1 = V
IH
or CE2 = V
IL
,
V
CC
= Max,
V
out
= GND to V
CC
1
1
1
1
A
Operating power
supply current
I
CC
CE1 = V
IL
, CE2 = V
IH
,
f = f
max,
I
out
= 0 mA
AS7C1024
175
160
120
110
mA
AS7C31024
100
70
65
mA
Standby
power supply
current
I
SB
CE1 = V
IH
or CE2 = V
IL
,
f = f
max
55
50
40
40
mA
I
SB1
CE1
V
CC
0.2V or CE2
0.2
V,
V
in
0.2V or V
in
V
CC
0.2V,
f = 0
10
10
10
10
mA
Output voltage
V
OL
I
OL
= 8 mA, V
CC
= Min
0.4
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
CC
= Min
2.4
2.4
2.4
2.4
V
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
A, CE1, CE2, WE, OE V
in
= 0V
5
pF
I/O capacitance
C
I/O
I/O
V
in
= V
out
= 0V
7
pF
Parameter
Symbol
-10
-12
-15
-20
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
10
12
15
20
ns
Address access time
t
AA
10
12
15
20
ns
3
Chip enable (CE1) access time
t
ACE1
10
12
15
20
ns
3, 12
Chip enable (CE2) access time
t
ACE2
10
12
15
20
ns
3, 12
Output enable (OE) access time
t
OE
3
3
4
5
ns
Output hold from address change
t
OH
2
3
3
3
ns
5
CE1 LOW to output in Low Z
t
CLZ1
3
3
3
3
ns
4, 5, 12
CE2 HIGH to output in Low Z
t
CLZ2
3
3
3
3
ns
4, 5, 12
CE1 HIGH to output in High Z
t
CHZ1
3
3
4
5
ns
4, 5, 12
CE2 LOW to output in High Z
t
CHZ2
3
3
4
5
ns
4, 5, 12
OE LOW to output in Low Z
t
OLZ
0
0
0
0
ns
4, 5
OE HIGH to output in High Z
t
OHZ
3
3
4
5
ns
4, 5
Power up time
t
PU
0
0
0
0
ns
4, 5, 12
Power down time
t
PD
10
12
15
20
ns
4, 5, 12
AS7C1024
AS7C31024
4
DID F11-20000-*A. 5/29/97
Copyright 1997 Alliance Semiconductor. All rights reserved.
Key to switching waveforms
Read waveform 1
3,6,7,9,12
Address controlled
Read waveform 2
3,6,8,9,12
CE1 and CE2 controlled
Write cycle
11, 12
Shaded areas contain advance information.
Parameter
Symbol
-10
-12
-15
-20
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Write cycle time
t
WC
10
12
15
20
ns
Chip enable (CE1) to write end
t
CW1
9
10
12
12
ns
12
Chip enable (CE2) to write end
t
CW2
9
10
12
12
ns
12
Address setup to write end
t
AW
9
10
12
12
ns
Address setup time
t
AS
0
0
0
0
ns
12
Write pulse width
t
WP
7
8
9
12
ns
Address hold from end of write
t
AH
0
0
0
0
ns
Data valid to write end
t
DW
6
6
9
10
ns
Data hold time
t
DH
0
0
0
0
ns
4, 5
Write enable to output in High Z
t
WZ
5
5
5
5
ns
4, 5
Output active from write end
t
OW
3
3
3
3
ns
4, 5
Undefined output/don't care
Falling input
Rising input
Address
D
out
Data valid
t
OH
t
AA
t
RC
supply
Current
CE2
OE
D
out
t
OE
t
OLZ
t
ACE1,
t
ACE2
t
CHZ1,
t
CHZ2
t
CLZ1,
t
CLZ2
t
PU
t
PD
I
CC
I
SB
50%
50%
t
OHZ
Data valid
t
RC
1
CE1
AS7C1024
AS7C31024
5
DID F11-20000-*A. 5/29/97
Copyright 1997 Alliance Semiconductor. All rights reserved.
Write waveform 1
10,11,12
WE controlled
Write waveform 2
10,11,12
CE1 and CE2 controlled
Data retention characteristics
14
Data retention waveform
Parameter
Symbol
Test conditions
Min
Max
Unit
V
CC
for data retention
V
DR
V
CC
= 2.0V
CE1
V
CC
0.2V or
CE2
0.2V
V
in
V
CC
0.2V or
V
in
0.2V
2.0
V
Data retention current
I
CCDR
500
A
Chip deselect to data retention time
t
CDR
0
ns
Operation recovery time
t
R
t
RC
ns
Input leakage current
|
I
LI
|
1
A
t
AW
t
AH
t
WC
Address
WE
D
out
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
in
t
AW
Address
CE1
WE
D
out
t
CW1,
t
CW2
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
CE2
Data valid
D
in
V
CC
CE
t
R
t
CDR
Data retention mode
4.5V
4.5V
V
DR
2.0V
V
IH
V
IH
V
DR
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