Document Outline
- Features
- Logic block diagram
- Pin arrangement
- Selection guide
- Functional description
- Absolute maximum ratings
- Truth table
- Recommended operating conditions
- DC operating characteristics (over the operating range)1
- Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2
- Read cycle (over the operating range)3,9
- Key to switching waveforms
- Read waveform 1 (address controlled)3,6,7,9
- Read waveform 2 (CE and OE controlled)3,6,8,9
- Write cycle (over the operating range)11
- Write waveform 1 (WE controlled)10,11
- Write waveform 2 (CE controlled)10,11
- AC test conditions
- Notes
- Package dimensions
- Ordering Codes
- Note: Add suffix N to the above part number for LEAD FREE parts. (Ex AS7C1025B-10TJCN)
- Part numbering system
March 2004
Copyright Alliance Semiconductor. All rights reserved.
AS7C1025B
5V 128K X 8 CMOS SRAM (Center power and ground)
3/26/04, v. 1.3
Alliance Semiconductor
P. 1 of 9
Features
Industrial and commercial temperatures
Organization: 131,072 x 8 bits
High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
Low power consumption: ACTIVE
- 605mW / max @ 10 ns
Low power consumption: STANDBY
- 55 mW / max CMOS
6 T 0.18 u CMOS technology
Easy memory expansion with CE, OE inputs
Center power and ground
TTL/LVTTL-compatible, three-state I/O
JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
ESD protection
2000 volts
Latch-up current
200 mA
Logic block diagram
512 x 256 x 8
Array
(1,048,576)
Se
nse a
m
p
Input buffer
A10 A1
1
A12 A13 A14 A15 A16
I/O0
I/O7
OE
CE
WE
Column decoder
Row de
code
r
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
V
CC
I/O5
I/O4
A12
A11
A10
A9
A8
A0
A1
A2
A3
CE
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
AS7C10
25B
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
Selection guide
-10
-12
-15
-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
7
8
ns
Maximum operating current
110
100
90
80
mA
Maximum CMOS standby current
10
10
10
10
mA
AS7C1025B
3/26/04, v. 1.3
Alliance Semiconductor
P. 2 of 9
Functional description
The AS7C1025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8
bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5/6/7/8 ns are ideal for high-
performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume I
SB
power. If the bus is static, then full
standby power is reached (I
SB1
). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O7 is written on
the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after
outputs have been disabled with
output enable (
OE
) or write enable
(WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025B is packaged in common
industry standard packages.
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Key: X = don't care, L = low, H = high.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on V
CC
relative to GND
V
t1
0.50
+7.0
V
Voltage on any pin relative to GND
V
t2
0.50
V
CC
+ 0.5
V
Power dissipation
P
D
1.0
W
Storage temperature (plastic)
T
stg
65
+150
o
C
Ambient temperature with V
CC
applied
T
bias
55
+125
o
C
DC current into outputs (low)
I
OUT
20
mA
Truth table
CE
WE
OE
Data
Mode
H
X
X
High Z
Standby (I
SB
, I
SB1
)
L
H
H
High Z
Output disable (I
CC
)
L
H
L
D
OUT
Read (I
CC
)
L
L
X
D
IN
Write (I
CC
)
AS7C1025B
3/26/04, v. 1.3
Alliance Semiconductor
P. 3 of 9
V
IL
min = -1.0V for pulse width less than 5ns
V
IH
max = V
CC
+2.0V for pulse width less than 5ns.
Recommended operating conditions
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage
V
CC
4.5
5.0
5.5
V
Input voltage
V
IH
2.2
V
CC
+ 0.5
V
V
IL
0.5
0.8
V
Ambient operating temperature
commercial
T
A
0
70
o
C
industrial
T
A
40
85
o
C
DC operating characteristics (over the operating range)
1
Parameter
Symbol
Test conditions
-10
-12
-15
-20
Unit
Min Max Min Max Min Max Min Max
Input leakage current
| I
LI
|
V
CC
= Max, V
IN
= GND to V
CC
1
1
1
1
A
Output leakage
current
| I
LO
|
V
CC
= Max, CE = V
IH
,
V
out
= GND to V
CC
1
1
1
1
A
Operating power
supply current
I
CC
V
CC
= Max
CE
V
IL
, f = f
Max,
I
OUT
= 0 mA
110
100
90
80
mA
Standby power supply
current
1
I
SB
V
CC
= Max
CE
V
IH
, f = f
Max
50
45
45
40
mA
I
SB1
V
CC
= Max
CE
V
CC
0.2 V,
V
IN
0.2 V or V
IN
V
CC
0.2 V,
f = 0
10
10
10
10
mA
Output voltage
V
OL
I
OL
= 8 mA, V
CC
= Min
0.4
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
CC
= Min
2.4
2.4
2.4
2.4
V
Capacitance (
f = 1 MHz, T
a
= 25
o
C, V
CC
= NOMINAL
)
2
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
A, CE, WE, OE
V
IN
= 0 V
5
pF
I/O capacitance
C
I/O
I/O
V
IN
= V
OUT
= 0 V
7
pF
AS7C1025B
3/26/04, v. 1.3
Alliance Semiconductor
P. 4 of 9
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Read waveform 2 (CE and OE controlled)
3,6,8,9
Read cycle (over the operating range)
3,9
Parameter
Symbol
-10
-12
-15
-20
Unit
Notes
Min Max Min Max Min Max Min Max
Read cycle time
t
RC
10
-
12
15
20
ns
Address access time
t
AA
-
10
12
15
20
ns
3
Chip enable (CE) access time
t
ACE
-
10
12
15
20
ns
3
Output enable (OE) access time
t
OE
-
5
6
7
8
ns
Output hold from address change
t
OH
3
-
3
3
3
ns
5
CE
low t
o output in low Z
t
CLZ
3
-
3
3
3
ns
4, 5
CE low to output in high Z
t
CHZ
-
4
5
6
7
ns
4, 5
OE low to output in low Z
t
OLZ
0
-
0
0
0
ns
4, 5
OE high to output in high Z
t
OHZ
-
4
5
6
7
ns
4, 5
Power up time
t
PU
0
-
0
0
0
ns
4, 5
Power down time
t
PD
-
10
12
15
20
ns
4, 5
Undefined/don't care
Falling input
Rising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
current
Supply
OE
D
OUT
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50%
50%
Data valid
t
RC1
CE
t
OHZ
AS7C1025B
3/26/04, v. 1.3
Alliance Semiconductor
P. 5 of 9
Write waveform 1 (WE controlled)
10,11
Write cycle (over the operating range)
11
Parameter
Symbol
-10
-12
-15
-20
Unit
Notes
Min Max Min Max Min Max Min Max
Write cycle time
t
WC
10
-
12
15
20
ns
Chip enable (CE) to write end
t
CW
8
-
9
10
12
ns
Address setup to write end
t
AW
8
-
9
10
10
ns
Address setup time
t
AS
0
-
0
0
0
ns
Write pulse width
t
WP
7
-
8
9
12
ns
Write recovery time
t
WR
0
-
0
0
0
ns
Address hold from end of write
t
AH
0
-
0
0
0
ns
Data valid to write end
t
DW
5
-
6
8
10
ns
Data hold time
t
DH
0
-
0
0
0
ns
4, 5
Write enable to output in high Z
t
WZ
-
5
6
7
8
ns
4, 5
Output active from write end
t
OW
1
-
1
1
2
ns
4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
PDF 
ZIP