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Электронный компонент: AS7C256A-12TCN

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September 2004
Copyright Alliance Semiconductor. All rights reserved.
AS7C256A
9/24/04; v.1.2
Alliance Semiconductor
P. 1 of 9
5V 32K X 8 CMOS SRAM (Common I/O)
Features
Pin compatible with AS7C256
Industrial and commercial temperature options
Organization: 32,768 words 8 bits
High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
Very low power consumption: ACTIVE
- 412.5 mW max @ 10 ns
Very low power consumption: STANDBY
- 11 mW max CMOS I/O
Easy memory expansion with CE and OE inputs
TTL-compatible, three-state I/O
28-pin JEDEC standard packages
- 300 mil SOJ
- 8
13.4 mm TSOP 1
ESD protection
2000 volts
Latch-up current
200 mA
2.0V Data retention
Logic block diagram
A
9
A
8
256 X 128 X 8
Array
(262,144)
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A
10
A
11
A
12
A
13
A
14
I/O0
I/O7
V
CC
GND
OE
CE
WE
Column decoder
Row decode
r
Control
circuit
S
e
ns
e
amp
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
AS7C256A
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
AS7C
256A
16
15
28-pin TSOP 1 (813.4 mm)
28-pin SOJ (300 mil)
Selection guide
-10
-12
-15
-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
7
8
ns
Maximum operating current
75
70
65
60
mA
Maximum CMOS standby current
2
2
2
2
mA
AS7C256A
9/24/04; v.1.2
Alliance Semiconductor
P. 2 of 9
Functional description
The AS7C256A is a 5.0V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized
as 32,768 words 8 bits. It is designed for memory applications requiring fast data access at low voltage, including
Pentium
TM
, PowerPC
TM
, and portable computing. Alliance's advanced circuit design and process techniques permit 5.0V
operation without sacrificing performance or operating margins.
The device enters standby mode when
CE
is high. CMOS standby mode consumes
11 mW. Normal operation offers 75%
power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5, 6, 7, 8 ns
are ideal for high-performance applications. The chip enable (
CE
) input permits easy memory expansion with multiple-bank
memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7
is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should
drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (
CE
) and output enable (
OE
) LOW, with write enable (
WE
) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0 0.5V supply. The AS7C256A is packaged
in high volume industry standard packages.
Absolute maximum ratings
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key
:
X = Don't care, L = Low, H = High
Parameter
Symbol
Min
Max
Unit
Voltage on V
CC
relative to GND
V
t1
0.5
+7.0
V
Voltage on any pin relative to GND
V
t2
0.5
V
CC
+ 0.5
V
Power dissipation
P
D
1.0
W
Storage temperature (plastic)
T
stg
65
+150
o
C
Ambient temperature with V
CC
applied
T
bias
55
+125
o
C
DC current into outputs (low)
I
OUT
20
mA
CE
WE
OE
Data
Mode
H
X
X
High Z
Standby (I
SB
, I
SB1
)
L
H
H
High Z
Output disable (I
CC
)
L
H
L
D
OUT
Read (I
CC
)
L
L
X
D
IN
Write (I
CC
)
AS7C256A
9/24/04; v.1.2
Alliance Semiconductor
P. 3 of 9
Recommended operating conditions
* V
IL
min = 1.0V for pulse width less than 5ns.
** V
IH
max = V
CC
+ 2.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)
1
Capacitance (f = 1MHz, T
a
= room temperature, V
CC
= NOMINAL)
4
Parameter
Symbol
Min
Typical
Max
Unit
Supply voltage
V
CC
4.5
5.0
5.5
V
Input voltage
V
IH
**
2.2
V
CC
+0.5
V
V
IL
*
-0.5
0.8
V
Ambient operating temperature
commercial
T
A
0
70
o
C
industrial
T
A
40
85
o
C
Parameter
Sym
Test conditions
-10
-12
-15
-20
Unit Notes
Min Max Min Max Min Max Min Max
Input leakage
current
|I
LI
| V
CC
= Max,
V
in
= GND to V
CC
1
1
1
1
A
Output leakage
current
|I
LO
| V
CC
= Max,
V
OUT
= GND to V
CC
1
1
1
1
A
Operating
power supply
current
I
CC
V
CC
= Max, CE
< V
IL
f = f
Max
, I
OUT
= 0mA
75
-
70
65
60
mA
Standby power
supply current
I
SB
V
CC
= Max, CE
> V
IH
f = f
Max
45
45
40
40
mA
I
SB1
V
CC
= Max, CE
> V
CC
0.2V
V
IN
< 0.2V or
V
IN
> V
CC
0.2V, f = 0
2.0
2.0
2.0
2.0
mA
Output voltage
V
OL
I
OL
= 8 mA, V
CC
= Min
0.4
0.4
0.4
0.4
V
4
V
OH
I
OH
= 4 mA, V
CC
= Min
2.4
2.4
2.4
2.4
V
4
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
A, CE, WE, OE
V
in
= 0V
5
pF
I/O capacitance
C
I/O
I/O
V
in
= V
out
= 0V
7
pF
AS7C256A
9/24/04; v.1.2
Alliance Semiconductor
P. 4 of 9
Read cycle (over the operating range)
2,8
Key to switching waveforms
Read waveform 1 (address controlled)
2,5,6,8
Read waveform 2 (CE controlled)
2,5,7,8
Parameter
Symbol
-10
-12
-15
-20
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
10
12
15
20
ns
Address access time
t
AA
10
12
15
20
ns
2
Chip enable (CE) access time
t
ACE
10
12
15
20
ns
2
Output enable (OE) access time
t
OE
5
6
7
8
ns
Output hold from address change
t
OH
3
3
3
3
ns
4
CE LOW to output in low Z
t
CLZ
3
3
3
3
ns
3,4
CE HIGH to output in high Z
t
CHZ
3
3
4
5
ns
3,4
OE LOW to output in low Z
t
OLZ
0
0
0
0
ns
3,4
OE HIGH to output in high Z
t
OHZ
3
3
4
5
ns
3,4
Power up time
t
PU
0
0
0
0
ns
3,4
Power down time
t
PD
10
12
15
20
ns
3,4
Undefined output/don't care
Falling input
Rising input
Address
D
out
Data valid
t
OH
t
AA
t
RC
Supply
current
CE
OE
D
out
t
RC
1
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50%
50%
t
OHZ
Data valid
AS7C256A
9/24/04; v.1.2
Alliance Semiconductor
P. 5 of 9
Write cycle (over the operating range)
9
Write waveform 1 (WE controlled)
9
Write waveform 2 (CE controlled)
9
Parameter
Symbol
-10
-12
-15
-20
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
Write cycle time
t
WC
10
12
15
20
ns
Chip enable to write end
t
CW
8
8
10
12
ns
Address setup to write end
t
AW
8
8
10
12
ns
Address setup time
t
AS
0
0
0
0
ns
Write pulse width
t
WP
7
8
9
12
ns
Write recovery time
t
WR
0
0
0
0
ns
Address hold from end of write
t
AH
0
0
0
0
ns
Data valid to write end
t
DW
5
6
8
10
ns
Data hold time
t
DH
0
0
0
0
ns
3,4
Write enable to output in high Z
t
WZ
5
6
7
8
ns
3,4
Output active from write end
t
OW
3
3
3
3
ns
3,4
t
AW
t
AH
t
WC
Address
WE
D
in
D
out
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
t
WR
t
AW
Address
CE
WE
D
in
Data valid
t
CW
t
DW
t
DH
t
AH
t
WC
t
AS
t
WR
AS7C256A
9/24/04; v.1.2
Alliance Semiconductor
P. 6 of 9
AC test conditions
Notes
1
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
2
For test conditions, see AC Test Conditions, Figures A, B.
3
These parameters are specified with CL = 5pF, as in Figures B. Transition is measured
500mV from steady-state voltage.
4
This parameter is guaranteed, but not tested.
5
WE is High for read cycle.
6
CE and OE are Low for read cycle.
7
Address valid prior to or coincident with CE transition Low.
8
All read cycle timings are referenced from the last valid address to the first transitioning address.
9
All write cycle timings are referenced from the last valid address to the first transitioning address.
10 C=30pF, except on High Z and Low Z parameters, where C=5pF.
255
C
10
480
D
out
GND
+5.0V
168
D
out
+1.72V
Figure B: Output load
Thevenin equivalent
- Output load: see Figure B
- Input pulse level: GND to V
CC
See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
10%
90%
10%
90%
GND
V
CC
Figure A: Input pulse
2 ns
AS7C256A
9/24/04; v.1.2
Alliance Semiconductor
P. 7 of 9
Package diagrams
28-pin SOJ
Min
Max
in inches
A
0.128
0.148
A1
0.026
-
A2
0.095
0.105
B
0.026
0.032
b
0.016
0.020
c
0.007
0.010
D
0.720
0.730
E
0.255
0.275
E1
0.295
0.305
E2
0.330
0.340
e
0.050 BSC
28-pin TSOP1
813.4 mm
Min
Max
A
1.00
1.20
A1
0.05
0.15
A2
0.91
1.05
b
0.17
0.27
c
0.10
0.20
D
11.70
11.90
e
0.55 nominal
E
7.90
8.10
Hd
13.20
13.60
L
0.50
0.70
0
5
e
D
E1
Pin 1
b
B
A1
A2
c
E
Seating
Plane
E2
A
e
b
E
Hd
D
c
L
A1
A
A2
28-pin SOJ
28-pin TSOP1
AS7C256A
9/24/04; v.1.2
Alliance Semiconductor
P. 8 of 9
Ordering information
Note: Add suffix `N'to the above part number for lead free parts. (Ex. AS7C256A-10JIN)
Part numbering system
Package / Access time
Temperature
10 ns
12 ns
15 ns
20 ns
Plastic SOJ, 300 mil
Commercial
AS7C256A-10JC
AS7C256A-12JC
AS7C256A-15JC
AS7C256A-20JC
Industrial
AS7C256A-10JI
AS7C256A-12JI
AS7C256A-15JI
AS7C256A-20JI
TSOP 8x13.4mm
Commercial
AS7C256A-10TC
AS7C256A-12TC
AS7C256A-15TC
AS7C256A-20TC
Industrial
AS7C256A-10TI
AS7C256A-12TI
AS7C256A-15TI
AS7C256A-20TI
AS7C
256A
XX
X
C or I
X
SRAM prefix Device number Access time
Packages:
J = SOJ 300 mil
T = TSOP 8x13.4mm
Temperature range:
C = 0
o
C to 70
0
C
I = -40C to 85C
N= Lead Free Part
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright Alliance Semiconductor
All Rights Reserved
Part Number: AS7C256A
Document Version: v.1.2
Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related
to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and
Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of
Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other
intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems
where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-
supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
AS7C256A