November 2004
Copyright Alliance Semiconductor. All rights reserved.
AS7C33512PFD18A
3.3V 512K
18 pipeline burst synchronous SRAM
12/1/04;
v.1.3
Alliance Semiconductor
1 of 20
Features
Organization: 524,288 words 18 bits
Fast clock speeds to 166 MHz
Fast clock to data access: 3.5/4.0 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous register-to-register operation
Dual-cycle deselect
Asynchronous output enable control
Individual byte write and global write
Available in 100-pin TQFP package
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Byte write enables
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Selection guide
166
133
Units
Minimum cycle time
6
7.5
ns
Maximum clock frequency
166
133
MHz
Maximum clock access time
3.5
4
ns
Maximum operating current
475
425
mA
Maximum standby current
130
100
mA
Maximum CMOS standby current (DC)
30
30
mA
Logic block diagram
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
19
17
19
A[18:0]
19
Address
D
Q
CS
CLK
register
512K 18
Memory
array
18
18
DQb
CLK
D
Q
Byte Write
registers
DQa
CLK
D
Q
Byte Write
registers
Enable
CLK
D
Q
register
Enable
CLK
D
Q
delay
register
CE
Output
registers
Input
registers
Power
down
2
CE0
CE1
CE2
BW
b
BW
a
OE
ZZ
OE
CLK
CLK
BWE
GWE
18
DQ[a,b]
AS7C33512PFD18A
12/1/04;
v.1.3
Alliance Semiconductor
2 of 20
8 Mb Synchronous SRAM products
list
1,2
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
PL-DCD
:
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT
:
Flow-through Burst Synchronous SRAM
NTD
1
-PL
:
Pipelined Burst Synchronous SRAM with NTD
TM
NTD-FT
:
Flow-through Burst Synchronous SRAM with NTD
TM
Org
Part Number
Mode
Speed
512KX18
AS7C33512PFS18A
PL-SCD
166/133 MHz
256KX32
AS7C33256PFS32A
PL-SCD
166/133 MHz
256KX36
AS7C33256PFS36A
PL-SCD
166/133 MHz
512KX18
AS7C33512PFD18A
PL-DCD
166/133 MHz
256KX32
AS7C33256PFD32A
PL-DCD
166/133 MHz
256KX36
AS7C33256PFD36A
PL-DCD
166/133 MHz
512KX18
AS7C33512FT18A
FT
7.5/8.5/10 ns
256KX32
AS7C33256FT32A
FT
7.5/8.5/10 ns
256KX36
AS7C33256FT36A
FT
7.5/8.5/10 ns
512KX18
AS7C33512NTD18A
NTD-PL
166/133 MHz
256KX32
AS7C33256NTD32A
NTD-PL
166/133 MHz
256KX36
AS7C33256NTD36A
NTD-PL
166/133 MHz
512KX18
AS7C33512NTF18A
NTD-FT
7.5/8.5/10 ns
256KX32
AS7C33256NTF32A
NTD-FT
7.5/8.5/10 ns
256KX36
AS7C33256NTF36A
NTD-FT
7.5/8.5/10 ns
1. NTD: No Turnaround Delay. NTD
TM
is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the prop-
erty of their respective owners.
AS7C33512PFD18A
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Alliance Semiconductor
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Functional description
The AS7C33512PFD18A is a high performance CMOS 8-Mbit Synchronous Static Random Access Memory (SRAM) devices organized as
524,288 words 18 bits and incorporate a pipeline for highest frequency on any given technology.
Fast cycle times of 6/7.5 ns with clock access times (t
CD
) of 3.5/4.0 ns enable 166 and 133 MHz bus frequencies. Three chip enable inputs
permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor
address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and
driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on
all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address
strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium
1
count sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPC
TM
and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented
internally to the next burst address if BWn and ADV are sampled LOW.
This device operates in double-cycle deselect feature during
read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are
as follows:
ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C33512PFD18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are
available in a 100-pin 1420 mm TQFP packaging.
.
*Guaranteed not tested
1. PowerPC
TM
is a trademark International Business Machines Corporation
Capacitance
Parameter
Symbol
Test conditions
Max
Unit
Input capacitance
C
IN
*
V
IN
= 0V
5
pF
I/O capacitance
C
I/O
*
V
IN
= V
OUT
= 0V
7
pF
TQFP thermal resistance
Description
Conditions
Symbol
Typical
Units
Thermal resistance
(junction to ambient)
1
1 This parameter is sampled.
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
1layer
JA
40
C/W
4layer
JA
22
C/W
Thermal resistance
(junction to top of case)
1
JC
8
C/W
AS7C33512PFD18A
12/1/04;
v.1.3
Alliance Semiconductor
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Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
PUS
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
Signal descriptions
Signal
I/O Properties
Description
CLK
I
CLOCK
Clock. All inputs except OE, ZZ,
LBO
are synchronous to this clock.
A,A0,A1
I
SYNC
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
DQ[a,b]
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0
I
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
CE1, CE2
I
SYNC
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
ADSP
I
SYNC
Address strobe (processor). Asserted LOW to load a new address or to enter standby mode.
ADSC
I
SYNC
Address strobe (controller). Asserted LOW to load a new address or to enter standby mode.
ADV
I
SYNC
Burst advance. Asserted LOW to continue burst read/write.
GWE
I
SYNC
Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE and BW[a,b]
control write enable.
BWE
I
SYNC
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs.
BW[a,b]
I
SYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
OE
I
ASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
LBO
I
STATIC
Selects Burst mode. When tied to V
DD
or left floating, device follows Interleaved Burst
order. When driven Low, device follows linear Burst order. This signal is internally pulled
High.
ZZ
I
ASYNC
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC
-
-
No connect
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