ASM5P23S09A
November 2004
ASM5P23S05A
rev 1.3
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
REF
ASM5P23S05A
3.3V `SpreadTrak' Zero Delay Buffer
General Features
15 MHz to 133 MHz operating range, compatible
with CPU and PCI bus frequencies.
Zero input - output propagation delay.
Multiple low-skew outputs.
Output-output skew less than 250 pS.
Device-device skew less than 700 pS.
One input drives 9 outputs, grouped as 4+4+1
(ASM5P23S09A).
One input drives 5 outputs (ASM5P23S05A).
Less than 200 pS cycle-to-cycle jitter is compatible
with Pentium
based systems.
Test Mode to bypass PLL (ASM5P23S09A only,
refer Select Input Decoding Table).
Available in 16-pin, 150-mil SOIC and 4.4 mm
TSSOP packages for ASM5P23S09A and in
8-pin, 150-mil SOIC and 4.4 mm TSSOP
packages for ASM5P23S05A.
3.3V operation
Advanced 0.35< CMOS technology.
`SpreadTrak'.
Functional Description
ASM5P23S09A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks with Spread
Spectrum capability. It is available in a 16-pin package. The
ASM5P23S05A is the eight-pin version of the
ASM5P23S09A. It accepts one reference input and drives
out five low-skew clocks.
The -1H version of the ASM5P23SxxA operates at up to
133 MHz frequency, and has higher drive than the -1
device. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The ASM5P23S09A has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. If all the output clocks are
not required, Bank B can be three-stated. The select input
also allows the input clock to be directly applied to the
outputs for chip and system testing purposes.
Multiple ASM5P23S09A and ASM5P23S05A devices can
accept the same input clock and distribute it. In this case
the skew between the outputs of the two devices is
guaranteed to be less than 700 pS.
All outputs have less than 200 pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250 pS, and the output to output skew is
guaranteed to be less than 250 pS.
The ASM5P23S09A and the ASM5P23S05A are available
in two different configurations, as shown in the ordering
information table. The ASM5P23SxxA-1 is the base part.
The ASM5P23SxxA-1H is the high drive version of the -1
part and its rise and fall times are much faster than -1 part.
Block Diagram
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLKOUT
REF
S1
S2
Select Input
MUX
ASM5P23S09A
Decoding
PLL
ASM5P23S09A
November 2004
ASM5P23S05A
rev 1.3
3.3V `SpreadTrak' Zero Delay Buffer
2 of 18
Notice: The information in this document is subject to change without notice.
Select Input Decoding for ASM5P23S09A
S2
S1
Clock A1 - A4
Clock B1 - B4
CLKOUT
1
Output Source
PLL
Shut-Down
0
0
Three-state Three-state Driven
PLL
N
0
1
Driven Three-state
Driven PLL
N
1
0
Driven Driven
Driven
Reference Y
1
1
Driven Driven
Driven
PLL
N
Note:
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the
output.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input-output delay.
For applications requiring zero input-output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero-input-output
delay.
SpreadTrak
Many systems being designed now utilize a technology
called Spread Spectrum Frequency Timing Generation.
ASM5P23S09A and ASM5P23S05A are designed so as
not to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero delay
buffer is not designed to pass the Spread Spectrum feature
through, the result is a significant amount of tracking skew
which may cause problems in the systems requiring
synchronization.
ASM5P23S09A
November 2004
ASM5P23S05A
rev 1.3
3.3V `SpreadTrak' Zero Delay Buffer
3 of 18
Notice: The information in this document is subject to change without notice.
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
V
DD
GND
S2
CLKOUT
S1
GND
V
DD
ASM5P23S09A
1
2
3
4
5
6
7
8
REF
CLK2
CLK1
CLK4
CLK3
V
DD
CLKOUT
GND
ASM5P23S05A
ASM5P23S09A
November 2004
ASM5P23S05A
rev 1.3
3.3V `SpreadTrak' Zero Delay Buffer
4 of 18
Notice: The information in this document is subject to change without notice.
Pin Description for ASM5P23S09A
Pin #
Pin Name
Description
1
REF
2
Input reference frequency, 5V tolerant input
2
CLKA1
3
Buffered clock output, bank A
3
CLKA2
3
Buffered clock output, bank A
4
V
DD
3.3V
supply
5
GND Ground
6
CLKB1
3
Buffered clock output, bank B
7
CLKB2
3
Buffered clock output, bank B
8
S2
4
Select input, bit 2
9
S1
4
Select input, bit 1
10 CLKB3
3
Buffered clock output, bank B
11 CLKB4
3
Buffered clock output, bank B
12 GND
Ground
13 V
DD
3.3V
supply
14 CLKA3
3
Buffered clock output, bank A
15 CLKA4
3
Buffered clock output, bank A
16 CLKOUT
3
Buffered output, internal feedback on this pin
Pin Description for ASM5P23S05A
Pin #
Pin Name
Description
1
REF
2
Input reference frequency, 5V-tolerant input
2
CLK2
3
Buffered clock output
3
CLK1
3
Buffered clock output
4
GND Ground
5
CLK3
3
Buffered clock output
6
V
DD
3.3V
supply
7
CLK4
3
Buffered clock output
8
CLKOUT
3
Buffered clock output, internal feedback on this pin
Notes:
2. Weak pull-down.
3. Weak pull-down on all outputs.
4. Weak pull-up on these inputs.
ASM5P23S09A
November 2004
ASM5P23S05A
rev 1.3
3.3V `SpreadTrak' Zero Delay Buffer
5 of 18
Notice: The information in this document is subject to change without notice.
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
-0.5
+7.0
V
DC Input Voltage (Except REF)
-0.5
VDD + 0.5
V
DC Input Voltage (REF)
-0.5
7
V
Storage Temperature
-65
+150
C
Max. Soldering Temperature (10 sec)
260
C
Junction Temperature
150
C
Static Discharge Voltage
(per MIL-STD-883, Method 3015)
2000
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device
reliability.
Operating Conditions for ASM5P23S05A and ASM5P23S09A - Commercial Temperature Devices
Parameter
Description
Min
Max
Unit
V
DD
Supply
Voltage
3.0
3.6
V
T
A
Operating Temperature (Ambient Temperature)
0
70
C
C
L
Load Capacitance, below 100 MHz
30
pF
C
L
Load Capacitance, from 100 MHz to 133 MHz
10
pF
C
IN
Input
Capacitance
7
pF
Electrical Characteristics for ASM5P23S05A and ASM5P23S09A - Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
V
IL
Input LOW Voltage
5
0.8 V
V
IH
Input HIGH Voltage
5
2.0 V
I
IL
Input
LOW
Current
V
IN
= 0V
50.0
<A
I
IH
Input HIGH Current
V
IN
= V
DD
100.0
<A
V
OL
Output
LOW
Voltage
6
I
OL
= 8mA (-1)
I
OH
= 12mA (-1H)
0.4 V
V
OH
Output HIGH Voltage
6
I
OL
= -8mA (-1)
I
OH
= -12mA (-1H)
2.4 V
I
DD
Supply Current
Unloaded outputs at
66.67 MHz, SEL inputs at V
DD
34 mA
Z
O
Output Impedance
23
K
Notes:
5. REF input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production
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