www.docs.chipfind.ru
July 2005
ASM5I9352
rev 0.2
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer
Features
Output frequency range: 25MHz to 200MHz
Output frequency range: 16.67MHz to 200MHz
Input frequency range: 16.67MHz to 200MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
2% max Output duty cycle variation
11 Clock outputs: Drive up to 22 clock lines
LVCMOS reference clock input
125-pS max output-output skew
PLL bypass mode
Spread
Aware
TM
Output
enable/disable
Pin compatible with MPC9352 and MPC952
Industrial temperature range: 40C to +85C
32-Pin 1.0mm TQFP & LQFP Packages
Functional Description
The ASM5I9352 is a low voltage high performance
200MHz PLL-based zero delay buffer designed for high
speed clock distribution applications.
The ASM5I9352 features an LVCMOS reference clock
input and provides 11 outputs partitioned in 3 banks of 5, 4,
and 2 outputs. Bank A divides the VCO output by 4 or 6
while Bank B divides by 4 and 2 and Bank C divides by 2
and 4 per SEL(A:C) settings, see Table 2. These dividers
allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and
1:3. Each LVCMOS compatible output can drive 50 series
or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:22.
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide
range of output frequencies from 16.67 MHz to 200 MHz.
For normal operation, the external feedback input, FB_IN,
is connected to one of the outputs. The internal VCO is
running at multiples of the input reference clock set by the
feedback divider, see Table 1.
When PLL_EN# is HIGH, PLL is bypassed and the
reference clock directly feeds the output dividers. This
mode is fully static and the minimum input clock frequency
specification does not apply.
July 2005
ASM5I9352
rev 0.2
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
2 of
12
Notice: The information in this document is subject to change without notice.
Block Diagram
Pin Configuration
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
PLL_EN#
+2
QA4
QC0
QC1
+4/
+6
+4/
+2
+2/
+4
VCO
200-500MHz
Phase
Detector
LPF
REFCLK
FB_IN
VCO_SEL
SELA
SELB
SELC
MR/OE#
QA0
QA1
VDDQA
VSS
QB3
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
24
23
22
21
20
19
18
17
SELC
SELB
SELA
MR/OE#
REFCLK
AVSS
FB_IN
VCO_SEL
VDDQC
QC0
VSS
QB2
VDDQB
PLL_
EN#
AVDD
VDD
VSS
QA2
QA4
VDDQA
VDDQB
QB0
QB1
VSS
QA3
VSS
ASM5I9352
QC1
July 2005
ASM5I9352
rev 0.2
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
3 of
12
Notice: The information in this document is subject to change without notice.
Pin Configuration
1
Pin
Name
I/O
Type
Description
6 REFCLK
I,
PD
LVCMOS
Reference clock input
.
12, 14,
15, 18, 19
QA(0:4) O
LVCMOS
Clock output bank A
.
22, 23,
26, 27
QB(0:3) O
LVCMOS
Clock output bank B
.
30, 31
QC(0,1)
O
LVCMOS
Clock output bank C
.
8 FB_IN I,
PD
LVCMOS
Feedback clock input
. Connect to an output for normal operation.
This input should be at the same voltage rail as input reference
clock. See
Table 1
.
1 VCO_SEL
I,
PD
LVCMOS
VCO divider select input
. See
Table 2
.
5 MR/OE#
I,
PD
LVCMOS
Master reset/output enable/disable input
. See
Table 2
.
9 PLL_EN#
I,
PD
LVCMOS
PLL enable/disable input
. See Table 2.
2, 3, 4
SEL(A:C)
I, PD
LVCMOS
Frequency select input, Bank (A:C)
. See
Table 2
.
16, 20
V
DDQA
Supply V
DD
2.5V or 3.3V power supply for bank A output clocks
2,3
.
21, 25
V
DDQB
Supply V
DD
2.5V or 3.3V power supply for bank B output clocks
.
2,3
32 V
DDQC
Supply V
DD
2.5V or 3.3V power supply for bank C output clocks
.
2,3
10 AV
DD
Supply V
DD
2.5V or 3.3V power supply for PLL
.
2,3
11 V
DD
Supply V
DD
2.5V or 3.3V power supply for core and inputs
.
2,3
7 AV
SS
Supply Ground
Analog ground
.
13, 17,
24, 28, 29
V
SS
Supply Ground
Common ground
.
Note: 1. PD = Internal pull-down.
2.A 0.1F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins
their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3.AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output
supply pins.
July 2005
ASM5I9352
rev 0.2
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
4 of
12
Notice: The information in this document is subject to change without notice.
Table 1: Frequency Table
VCO_SEL
Feedback
Output Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency
Range (AVDD = 2.5V)
0
2
Input Clock * 2
100 MHz to 200 MHz
100 MHz to 200 MHz
0
4
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 100 MHz
0
6
Input Clock * 6
33.33 MHz to 83.33 MHz
33.33 MHz to 66.67 MHz
1
2
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 100 MHz
1
4
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 50 MHz
1
6
Input Clock * 12
16.67 MHz to 41.67 MHz
16.67 MHz to 33.33 MHz
Table 2: Function Table
Control
Default
0
1
VCO_SEL
0
VCO
VCO 2
PLL_EN# 0
PLL enabled. The VCO output
connects to the output dividers
Bypass mode, PLL disabled. The input clock
connects to the output dividers
MR/OE# 0
Outputs
enabled
Outputs disabled (three-state), VCO running
at its minimum frequency
SELA
0
QA = VCO4
QA = VCO6
SELB
0
QB = VCO 4
QB = VCO2
SELC
0
QC = VCO2
QC = VCO4
Absolute Maximum Ratings
Parameter
Description
Condition
Min
Max
Unit
V
DD
DC Supply Voltage
0.3 5.5 V
V
DD
DC Operating Voltage
Functional 2.375
3.465
V
V
IN
DC Input Voltage
Relative to V
SS
0.3 V
DD
+ 0.3
V
V
OUT
DC Output Voltage
Relative to V
SS
0.3 V
DD
+ 0.3
V
V
TT
Output termination Voltage
V
DD
2 V
LU
Latch Up Immunity
Functional
200
mA
R
PS
Power Supply Ripple
Ripple Frequency < 100 kHz
150 mVp-p
T
S
Temperature, Storage
Non Functional 65
+150
C
T
A
Temperature, Operating Ambient Functional
40 +85 C
T
J
Temperature, Junction
Functional
155 C
JC
Dissipation, Junction to Case
Functional
42 C/W
JA
Dissipation, Junction to Ambient
Functional
105 C/W
ESD
H
ESD Protection (Human Body Model)
2000
Volts
FIT
Failure in Time
Manufacturing test
10
ppm
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device
reliability.
July 2005
ASM5I9352
rev 0.2
2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer
5 of
12
Notice: The information in this document is subject to change without notice.
DC Electrical Specifications
(V
DD
= 2.5V 5%, T
A
= -40C to +85C)
Parameter
Description
Condition
Min
Typ
Max
Unit
V
IL
Input Voltage, Low
LVCMOS
0.7 V
V
IH
Input Voltage, High
LVCMOS
1.7
V
DD
+ 0.3
V
V
OL
Output Voltage, Low
1
I
OL
= 15 mA
0.6 V
V
OH
Output Voltage, High
1
I
OH
= 15 mA
1.8
V
I
IL
Input Current, Low
V
IL
= V
SS
10 A
I
IH
Input Current, High
2
V
IL
= V
DD
100 A
I
DDA
PLL Supply Current
AV
DD
only
5 10
mA
I
DDQ
Quiescent Supply Current
All V
DD
pins except AV
DD
3 5
mA
I
DD
Dynamic Supply Current
170
mA
C
IN
Input Pin Capacitance
4
pF
Z
OUT
Output Impedance
17 20
Note:1.Driving one 50 parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50 series terminated
transmission lines.
2.Inputs have pull-down resistors that affect the input current.
DC Electrical Specifications
(V
DD
= 3.3V 5%, T
A
= -40C to +85C)
Parameter
Description
Condition
Min
Typ
Max
Unit
V
IL
Input Voltage, Low
LVCMOS
0.8 V
V
IH
Input Voltage, High
LVCMOS
2.0
V
DD
+ 0.3
V
I
OL
= 24 mA
0.55
V
OL
Output Voltage, Low
1
I
OL
= 12 mA
0.30
V
V
OH
Output Voltage, High
1
I
OH
= 24 mA
2.4
V
I
IL
Input Current, Low
V
IL
= V
SS
10 A
I
IH
Input Current, High
2
V
IL
= V
DD
100 A
I
DDA
PLL Supply Current
AV
DD
only
5 10
mA
I
DDQ
Quiescent Supply Current
All V
DD
pins except AV
DD
3 5
mA
I
DD
Dynamic Supply Current
240
mA
C
IN
Input Pin Capacitance
4
pF
Z
OUT
Output Impedance
14 17
Note:1.Driving one 50 parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50 series terminated <
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