July 2005
ASM5I961C
rev 0.2
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
Low Voltage Zero Delay Buffer
Features
Fully Integrated PLL
Up to 200MHz I/O Frequency
LVCMOS
Outputs
Outputs Disable in High Impedance
LVCMOS Reference Clock Options
LQFP and TQFP Packaging
50pS CycleCycle Jitter
150pS Output Skews
Functional Description
The ASM5I961C is a 2.5V or 3.3V compatible, 1:18 PLL
based zero delay buffer. With output frequencies of up to
200MHz, output skews of 150pS the device meets the
needs of the most demanding clock tree applications.
The ASM5I961 is offered with two different input
configurations. The ASM5I961C offers an LVCMOS
reference clock while the ASM5I961P offers an LVPECL
reference clock.
When pulled high the OE pin will force all of the outputs
(except QFB) into a high impedance state. Because the OE
pin does not affect the QFB output, down stream clocks
can be disabled without the internal PLL losing lock.
The ASM5I961C is fully 2.5V or 3.3V compatible and
requires no external loop filter components. All control
inputs accept LVCMOS compatible levels and the outputs
provide low impedance LVCMOS outputs capable of
driving terminated 50 transmission lines. For series
terminated lines the ASM5I961C can drive two lines per
output giving the device an effective fanout of 1:36. The
device is packaged in a 32 lead LQFP and TQFP
Packages.
Block Diagram
Figure 1. ASM5I961C Logic Diagram
Q0
Q1
Q2
Q3
Q14
Q15
Q16
QFB
0
1
100-200 MHz
50-100 MHz
Ref
FB
PLL
50K
50K
50K
50K
CCLK
FB_IN
F_RANGE
OE
July 2005
ASM5I961C
rev 0.2
Low Voltage Zero Delay Buffer
2 of
15
Notice: The information in this document is subject to change without notice.
Pin Configuration
Figure 2. ASM5I961C 32-Lead Package Pinout (Top View)
Table 1: Pin Configuration
Pin #
Pin Name
I/O
Type
Function
2
CCLK
Input
LVCMOS
PLL reference clock signal
7 FB_IN
Input
LVCMOS
PLL feedback signal input, connect to a
QFB output
4 F_RANGE
Input
LVCMOS
PLL frequency range select
6
OE
Input LVCMOS
Output
enable/disable
31,30,29,27,26,25,23,22,21,
19,18,17,15,14,13,11,10
Q0 - Q16
Output
LVCMOS
Clock outputs
9 QFB
Output
LVCMOS
PLL feedback signal output, connect to a
FB_IN
1,12,20,28
GND
Supply
Ground
Negative power supply
5 VCCA
Supply
VCC
PLL positive power supply (analog power
supply). The ASM5I961C requires an
external RC filter for the analog power
supply pin V
CCA
. Please see applications
section for details.
8,16,24,32
VCC
Supply
VCC
Positive power supply for I/O and core
3 NC
Not connected
25
26
27
28
29
30
31
32
24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8
16
15
14
13
12
11
10
9
Q4
Q3
GND
Q2
Q1
Q0
VCC
Q5
VCC
Q6
Q7
Q8
GND
Q9
Q10
Q11
GND
CCL
K
NC
F_RANGE
VCCA
OE
FB_IN
VCC
Q15
GND
Q14
Q13
Q12
VCC
Q16
QFB
ASM5I961C
July 2005
ASM5I961C
rev 0.2
Low Voltage Zero Delay Buffer
3 of
15
Notice: The information in this document is subject to change without notice.
Table 2: FUNCTION TABLE
Control
Default
0
1
F_RANGE 0
PLL high frequency range. ASM5I961C input
reference and output clock frequency range is
100 200MHz
PLL low frequency range. ASM5I961C input
reference and output clock frequency range is
50 100MHz
OE
0
Outputs enabled
Outputs disabled (highimpedance state)
Table 3: ABSOLUTE MAXIMUM RATINGS
1
Symbol
Parameter
Min
Max
Unit
V
CC
Supply
Voltage
0.3
3.6
V
V
IN
DC Input Voltage
0.3
V
CC
+ 0.3
V
V
OUT
DC Output Voltage
0.3
V
CC
+ 0.3
V
I
IN
DC Input Current
20 mA
I
OUT
DC Output Current
50 mA
T
S
Storage Temperature Range
40
125
C
Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Table 4: DC CHARACTERISTICS
(V
CC
= 3.3V 5%, T
A
= -40C to +85C)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
V
IH
Input HIGH Voltage
2.0
VCC + 0.3
V
LVCMOS
V
IL
Input LOW Voltage
0.3
0.8 V LVCMOS
V
OH
Output HIGH Voltage
2.4
V I
OH
= 20mA
1
V
OL
Output LOW Voltage
0.55 V I
OL
= 20mA
1
Z
OUT
Output
Impedance
14 20
I
IN
Input
Current
120
A
C
IN
Input
Capacitance
4.0
pF
C
PD
Power Dissipation Capacitance
8.0 10
pF
Per
Output
I
CCA
Maximum PLL Supply Current
2.0 5.0
mA V
CCA
Pin
I
CC
Maximum Quiescent Supply Current
TBD
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