September 2005
ASM5P2308A
rev 1.4
Notice: The information in this document is subject to change without notice.
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
3.3V Zero-Delay Buffer
General Features
Zero input - output propagation delay, adjustable by
capacitive load on FBK input.
Multiple configurations - Refer "ASM5P2308A
Configurations " Table.
Input frequency range: 15MHz to 133MHz
Multiple low-skew outputs.
Output-output skew less than 200pS.
Device-device skew less than 700pS.
Two banks of four outputs, tri-stateable by two select
inputs.
Less than 200pS cycle-to-cycle jitter
(-1, -1H,-2, -3, -4, -5H).
Available in 16 pin SOIC and TSSOP packages.
3.3V operation.
Advanced 0.35 CMOS technology.
Industrial temperature available.
Functional Description
ASM5P2308A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It is available in a
16 pin package. The part has an on-chip PLL which locks
to an input clock presented on the REF pin. The PLL
feedback is required to be driven to FBK pin, and can be
obtained from one of the outputs. The input-to-output
propagation delay is guaranteed to be less than 250pS,
and the output-to-output skew is guaranteed to be less than
200pS.
The ASM5P2308A has two banks of four outputs each,
which can be controlled by the select inputs as shown in
the Select Input Decoding Table. The select input also
allows the input clock to be directly applied to the outputs
for chip and system testing purposes.
Multiple ASM5P2308A devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
700pS.
The ASM5P2308A is available in five different
configurations(Refer "ASM5P2308A Configurations" Table).
The ASM5P2308A-1 is the base part, where the output
frequencies equal the reference if there is no counter in the
feedback path. The ASM5P2308A-1H is the high-drive
version of the -1 and the rise and fall times on this device
are much faster.
The ASM5P2308A-2 allows the user to obtain 2X and 1X
frequencies on each output bank. The exact configuration
and output frequencies depends on which output drives the
feedback pin. The ASM5P2308A-3 allows the user to
obtain 4X and 2X frequencies on the outputs.
The ASM5P2308A-4 enables the user to obtain 2X clocks
on all outputs.
The ASM5P2308A-5H is a high-drive version with REF/2
on both banks. Thus, the part is extremely versatile, and
can be used in a variety of applications.
September 2005
ASM5P2308A
rev 1.4
3.3V Zero Delay Buffer
3 of 18
Notice: The information in this document is subject to change without notice.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay between input and output.
To close the feedback loop of the ASM5P2308A, the FBK pin can be driven from any of the eight available output pins. The
output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this
output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded.
If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback
output and remaining outputs. For zero output-output skew, be sure to load outputs equally.
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
0
-500
-1000
-1500
500
1000
1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
R
E
F-
In
p
u
t
to
C
L
K
A
/C
L
K
B
D
e
la
y
September 2005
ASM5P2308A
rev 1.4
3.3V Zero Delay Buffer
4 of 18
Notice: The information in this document is subject to change without notice.
Pin Configuration
Pin Description for ASM5P2308A
Pin #
Pin Name
Description
1 REF
3
Input reference frequency, 5V tolerant input
2 CLKA1
4
Buffered clock output, bank A
3 CLKA2
4
Buffered clock output, bank A
4 V
DD
3.3V
supply
5 GND
Ground
6 CLKB1
4
Buffered clock output, bank B
7 CLKB2
4
Buffered clock output, bank B
8 S2
5
Select input, bit 2
9 S1
5
Select input, bit 1
10 CLKB3
4
Buffered clock output, bank B
11 CLKB4
4
Buffered clock output, bank B
12 GND
Ground
13 V
DD
3.3V
supply
14 CLKA3
4
Buffered clock output, bank A
15 CLKA4
4
Buffered clock output, bank A
16
FBK
PLL feedback input
Notes:
3. Weak pull-down.
4. Weak pull-down on all outputs.
5. Weak pull-up on these inputs.
11
9
10
12
13
14
15
16
S2
2
1
3
4
5
6
7
8
V
DD
CLKA3
CLKB3
CLKB4
FBK
V
DD
GND
CLKB1
S1
CLKA1
REF
CLKB2
CLKA4
CLKA2
GND
ASM5P2308A
September 2005
ASM5P2308A
rev 1.4
3.3V Zero Delay Buffer
5 of 18
Notice: The information in this document is subject to change without notice.
Absolute Maximum Ratings
Operating Conditions for ASM5P2308A Commercial Temperature Devices
Parameter
Description
Min
Max
Unit
V
DD
Supply Voltage
3.0
3.6
V
T
A
Operating Temperature (Ambient Temperature)
0
70
C
C
L
Load Capacitance, below 100MHz
30
pF
C
L
Load Capacitance, from 100MHz to 133MHz
15
pF
C
IN
Input Capacitance
6
7
pF
Note:
6. Applies to both Ref Clock and FBK.
Electrical Characteristics for ASM5P2308A Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
V
IL
Input LOW Voltage
0.8
V
V
IH
Input HIGH Voltage
2.0
V
I
IL
Input LOW Current
V
IN
= 0V
50.0
A
I
IH
Input HIGH Current
V
IN
= V
DD
100.0
A
V
OL
Output LOW Voltage
7
I
OL
= 8mA (-1, -2, -3, -4)
I
OH
= 12mA (-1H, -5H)
0.4 V
V
OH
Output HIGH Voltage
7
I
OL
= -8mA (-1, -2, -3, -4)
I
OH
= -12mA (-1H, -5H)
2.4 V
(-2,-3,-4)
49
Unloaded outputs 100MHz REF
Select inputs at V
DD
or GND
(-1H,-5H)
60
Unloaded outputs, 66MHz REF (-1, -2, -3, -4)
34
I
DD
Supply
Current
8
Unloaded outputs, 33MHz REF (-1, -2, -3, -4)
18
mA
Note:
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. Supply Currents are measured for PLL-Bypass Mode (S2=1, S1=0)
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
-0.5
+7.0
V
DC Input Voltage (Except REF)
-0.5
V
DD
+ 0.5
V
DC Input Voltage (REF)
-0.5
7
V
Storage Temperature
-65
+150
C
Max. Soldering Temperature (10 sec)
260
C
Junction Temperature
150
C
Static Discharge Voltage (As per JEDEC STD22- A114-B)
2000
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device
reliability.
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