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November 2005
P1819
rev 1.7
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
Notebook LCD Panel EMI Reduction IC

Features
FCC approved method of EMI attenuation.
Provides up to 15dB EMI reduction.
Generates a low EMI Spread Spectrum clock and a
non-spread reference clock of the input frequency.
Optimized for Frequency range from 20 to 40MHz.
Internal loop filter minimizes external components
and board space.
Selectable spread options: Down and Center.
Low Inherent Cycle-to-Cycle jitter.
Eight spread % selections:
0.625% to 3.5%.
3.3V
0.3V Operating Voltage range.
Low power CMOS design.
Supports notebook VGA and other LCD timing
controller applications.
Power Down function for mobile application.
Available in Commercial temperature range.
Available in 8-pin SOIC and TSSOP Packages.

Product Description
The P1819 is a Versatile Spread Spectrum Frequency
Modulator designed specifically for input clock frequencies
from 20 to 40MHz. (Refer Input Frequency and Modulation
Rate Table).
The P1819 reduces electromagnetic
interference (EMI) at the clock source, allowing system
wide reduction of EMI of down stream clock and data
dependent signals. The P1819 allows significant system
cost savings by reducing the number of circuit board layers
ferrite beads, shielding and other passive components that
are traditionally required to pass EMI regulations.

The P1819 modulates the output of a single PLL in order to
"spread" the bandwidth of a synthesized clock, and more
importantly, decreases the peak amplitudes of its
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal's bandwidth is called `Spread
Spectrum Clock Generation'.
The P1819 uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.

Applications
The P1819 is targeted towards EMI management for
memory and LVDS interfaces in mobile graphic chipsets
and high-speed digital applications such as PC peripheral
devices, consumer electronics, and embedded controller
systems.


Block Diagram
VSS
VDD
ModOUT
XIN/CLKIN
Frequenc
y
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
VCO
Output
Divider
PLL
SRS
D_C/NC PD#
Crystal
Oscillator
XOUT
REF
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November 2005
P1819
rev 1.7
Note Book LCD Panel EMI Reduction IC
2 of 9
Notice: The information in this document is subject to change without notice.
VDD VDD

Pin Configuration














Pin Description
Pin#
1819A/B/C/D 1819E/F/G/H/Q
Pin Name
Type
Description
1
1
XIN / CLKIN
I
Crystal Connection or external frequency input.This pin
has dual functions. It can be connected to either an
external crystal or an external reference clock
2
2
VSS
P
Ground Connection. Connect to system ground.
3
SRS
I
Spread range select. Digital logic input used to select
frequency deviation (Refer Spread Deviation Selection
Table).
This pin has an internal pull-up resistor.
3
D_C / NC
I
Digital logic input used to select Down (LOW) or Center
(HIGH) spread options (Refer Spread Deviation
Selection Table).
This pin has an internal pull-up
resistor.
4 4
ModOUT
O
Spread spectrum clock output. (Refer Input Frequency
and Modulation Rate Table and Spread Deviation
Selection Table)
5 5
REF
O
Non-modulated Reference clock output of the input
frequency.
6 6
PD#
I
Power down control pin. Pull LOW to enable Power-
Down mode. This pin has an internal pull-up resistor.
7
7
VDD
P
Power Supply for the entire chip.
8 8
XOUT
O
Crystal Connection. Input connection for an external
crystal. If using an external reference, this pin must be
left unconnected.
Note: Pin 3 is NC in P1819Q


PD#
XOUT
REF
1
2
3
4
5
6
7
8
P1819 A/B/C/D
XIN/ CLKIN
VSS
SRS
ModOUT
REF
1
2
3
4
5
6
7
8
P1819 E/F/G/H/Q
XIN / CLKIN
VSS
D_C / NC
ModOUT
PD#
XOUT
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November 2005
P1819
rev 1.7
Note Book LCD Panel EMI Reduction IC
3 of 9
Notice: The information in this document is subject to change without notice.

Input Frequency and Modulation Rate
Part Number
Input Frequency Range
Output Frequency range
Modulation rate
P1819
20MHz to 40MHz
20MHz to 40MHz
Input Frequency / 512

Spread Deviation Selection
Part Number
SRS
D_C
Spread Deviation
0 -2.50%
(DOWN)
P1819A
1
NA
-3.50% (DOWN)
0 -1.25%
(DOWN)
P1819B
1
NA
-1.75% (DOWN)
0 1.25%
(CENTER)
P1819C
1
NA
1.75% (CENTER)
0 0.625%
(CENTER)
P1819D
1
NA
0.875% (CENTER)
0 -1.25%
(DOWN)
P1819E
NA
1 0.625%
(CENTER)
0 -2.5%
(DOWN)
P1819F NA
1 1.25%
(CENTER)
0 -1.75%
(DOWN)
P1819G NA
1 0.875%
(CENTER)
0 -3.5%
(DOWN)
P1819H NA
1 1.75%
(CENTER)
P1819Q NA
NA
-2.5%
(DOWN)

Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
V
DD
, V
IN
Voltage on any pin with respect to Ground
-0.5 to +7.0
V
T
STG
Storage temperature
-65 to +125
C
T
A
Operating temperature
0 to 70
C
T
s
Max. Soldering Temperature (10 sec)
260
C
T
J
Junction
Temperature
150
C
T
DV
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
2 KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.

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November 2005
P1819
rev 1.7
Note Book LCD Panel EMI Reduction IC
4 of 9
Notice: The information in this document is subject to change without notice.
DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+25C) unless otherwise stated)
Symbol
Parameter
Min
Typ
Max
Unit
V
IL
Input Low voltage
VSS 0.3
-
0.8
V
V
IH
Input High voltage
2.0
-
V
DD
+ 0.3
V
I
IL
Input Low current (inputs D_C, PD#, SRS)
-60.0
-
-20.0
A
I
IH
Input High current
-
-
1.0
A
I
XOL
X
OUT
Output low current @ 0.4V, V
DD
= 3.3V
2.0
-
12.0
mA
I
XOH
X
OUT
Output high current @ 2.5V, V
DD
= 3.3V
-
-
12.0
mA
V
OL
Output Low voltage V
DD
= 3.3V, I
OL
= 20mA
-
-
0.4
V
V
OH
Output High voltage V
DD
= 3.3V, I
OH
= 20mA
2.5
-
-
V
I
CC
Dynamic supply current normal mode
3.3V and 25pF probe loading
7.1
f
IN
- min
-
26.9
f
IN - max
mA
I
DD
Static supply current standby mode
-
4.5
-
mA
V
DD
Operating
Voltage 3.0
3.3
3.6
V
t
ON
Power up time (first locked clock cycle after power up)
-
0.18
-
mS
Z
OUT
Clock Output impedance
-
50
-

AC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
f
IN
Input Frequency
20
-
40
MHz
f
OUT
Output
Frequency
20
-
40
MHz
t
LH
*
Output Rise time
Measured from 0.8V to 2.0V
- 0.66
-
nS
t
HL
*
Output Fall time
Measured from 2.0V to 0.8V
- 0.65
-
nS
t
JC
Jitter (cycle to cycle)
-200
-
200
pS
t
D
Output Duty cycle
45
50
55
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF














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November 2005
P1819
rev 1.7
Note Book LCD Panel EMI Reduction IC
5 of 9
Notice: The information in this document is subject to change without notice.

Package Information
8-lead (150-mil) SOIC Package

D
E
H
D
A1
A2
A
L
C
B
e

Dimensions
Inches
Millimeters
Symbol
Min
Max
Min
Max
A1 0.004 0.010 0.10
0.25
A 0.053
0.069 1.35 1.75
A2 0.049 0.059 1.25
1.50
B 0.012
0.020 0.31 0.51
C 0.007
0.010 0.18 0.25
D
0.193 BSC
4.90 BSC
E
0.154 BSC
3.91 BSC
e
0.050 BSC
1.27 BSC
H
0.236 BSC
6.00 BSC
L 0.016
0.050 0.41 1.27
0 8 0 8

Note: Controlling dimensions are millimeters
SOIC 0.074 grams unit weight