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Электронный компонент: P2008A-08TT

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July 2005
P2008A
rev 1.3
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
General Purpose EMI Reduction IC

Features
FCC approved method of EMI attenuation.
Provides up to 15dB of EMI suppression.
Generates a 1X or X low EMI spread spectrum
clock of the input frequency.
Input frequency range: 4MHz to 32MHz.
Internal loop filter minimizes external components
and board space.
Spreading ranges from 0.8% to 3.2%.
SSON# control pin for spread spectrum enable
and disable options.
Low Cycle-to-Cycle jitter.
3.3V Operating Voltage.
Ultra-low power CMOS design.
Available in 8-pin SOIC and TSSOP Packages.

Product Description
The P2008A is a versatile spread spectrum frequency
modulator designed specifically for digital camera and
other digital video and imaging applications. The P2008A
reduces electromagnetic interference (EMI) at the clock
source, allowing system wide reduction of EMI of down
stream clock and data dependent signals. The P2008A
allows significant system cost savings by reducing the
number of circuit board layers ferrite beads, shielding
and other passive components that are traditionally
required to pass EMI regulations.

The P2008A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.

The P2008A modulates the output of a single PLL in
order to "spread" the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal's bandwidth is called `spread
spectrum clock generation'.

Applications
The P2008A is targeted towards cable, xDSL, fax
modem, set-top box, USB controller, DSC, and other
embedded systems.



Block Diagram
VSS
VDD
XIN/CLKIN
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
PLL
SSON#
DIV2
SR0
Crystal
Oscillator
XOUT

July 2005
P2008A
rev 1.3
General purpose EMI Reduction IC
2 of 9
Notice: The information in this document is subject to change without notice.
1
2
3
4
5
6
7
8
P2008A
XIN/ CLKIN
XOUT
DIV2
VSS
SSON#
ModOUT
SR0
VDD
Pin Configuration











Pin Description
Pin#
Pin Name
Type
Description
1 XIN/CLKIN I
Crystal connection or external reference frequency input. This pin has dual
functions. It can be connected either to an external crystal or an external
reference clock.
2 XOUT O
Crystal connection. If using an external reference, this pin must be left
unconnected.
3 DIV2 I
Digital logic input used to select normal output mode or divide-by-two output
mode. When this pin is HIGH, the frequency of the output clock is the same as the
input clock frequency. When it is tied low, the output frequency is half the input
clock frequency. This pin has an internal pull-up resistor.
4
VSS
P
Ground to entire chip. Connect to system ground.
5 SSON# I
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread
Spectrum function enabled when LOW, disabled when HIGH.
This pin has an internal pull-low resistor.
6
ModOUT
O
Spread spectrum clock output.
7 SR0 I
Digital logic input used to select Spreading Range (Refer Modulation Output and
Spreading Range Selection Table
.) This pin has an internal pull-up resistor.
8
VDD
P
Power supply for the entire chip


Modulation Output and Spreading Selection (ModOUT = XIN/CLKIN)
Output Frequency Range DIV2 = 1
Modulation Rate
SR0
8MHz 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz
0
2.2%
1.8%
1.2%
1.1%
1.0%
0.9%
0.8%
1
3.2%
2.5%
2.0%
1.6%
1.4%
1.25%
0.15%
(XIN/CLKIN/20) * 62.5 KHz
Modulation Output and Spreading Selection (ModOUT = XIN/CLKIN)
Output Frequency Range DIV2 = 0
Modulation Rate
SR0
4MHz 6MHz 8MHz 10MHz 12MHz 14MHz 16MHz
0
2.0%
1.8%
1.2%
1.1%
1.0%
0.9%
0.8%
1
3.2%
2.6%
2.0%
1.6%
1.4%
1.25%
0.15%
(XIN/CLKIN/20) * 62.5 KHz

July 2005
P2008A
rev 1.3
General purpose EMI Reduction IC
3 of 9
Notice: The information in this document is subject to change without notice.
Spread Spectrum
The Modulation Output and Spreading Selection Tables illustrate the two possible spread spectrum options. The optimal
setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a
percentage deviation of the center frequency (Note: The center frequency is the frequency of the external reference input on
XIN/CLKIN, Pin1).

Example:
The P2008A is designed for communications, digital video and imaging applications. It is not only optimized for operation in
the 4MHz 32MHz range, but its output frequency can be extended down to one half of the input clock frequency using the
divide-by-two feature. This feature extends low frequency as low as to 2MHz. Setting Pin 3 low (DIV2 = 0; Divide-by-two
mode) sets the output frequency (ModOUT) to half the frequency of the input clock (XIN/CLKIN). This is a simple way to
generate a spread spectrum modulated low frequency clock when only a higher frequency signal is available. If you want the
output frequency to be the same as the input, you can either set DIV2=1 or leave it unconnected.

Selecting the P2008A's spread options is a matter of either setting SR0=1 or SR0=0. Setting SR0=0 set as a lower
modulation spread, while setting it to 1 introduces a wider spectral spread in the output clock. Refer Modulation output and
Spreading Selections Tables.
The example given in the figure below shows the device set to the divide-by-two mode
(DIV2=0) with a lower spectrum range (SR0=0). The versatility provided by allowing both clock division and spread spectrum
on one chip is already proving to be a popular solution among leading system manufacturers.
P2008A Application Schematic

Modulated 4.416MHz is
connected to CLK input
pin of the system
1
2
3
4
XIN/CLKIN
XOUT
DIV2
VSS
SR0
5
6
7
8
SSON#
Mod OUT
VDD
8.832MHz Crystal
+3.3V
0.1F
P2008A

July 2005
P2008A
rev 1.3
General purpose EMI Reduction IC
4 of 9
Notice: The information in this document is subject to change without notice.
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
VDD, V
IN
Voltage on any pin with respect to Ground
-0.5 to +7.0
V
T
STG
Storage temperature
-65 to +125
C
T
A
Operating temperature
-40 to +85
C
T
s
Max. Soldering Temperature (10 sec)
260
C
T
J
Junction
Temperature
150
C
T
DV
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
2 KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.


DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
V
IL
Input low voltage
VSS 0.3
-
0.8
V
V
IH
Input high voltage
2.0
-
VDD + 0.3
V
I
IL
Input low current
(pull-up resistors on inputs SR0 and DIV2)
- -
-35
A
I
IH
Input high current (pull-down resistor on input SSON#)
-
-
35
A
I
XOL
XOUT Output Low Current (@ 0.4V, VDD = 3.3V)
-
3
-
mA
I
XOH
XOUT Output High Current (@ 2.5V, VDD = 3.3V)
-
3
-
mA
V
OL
Output low voltage (VDD = 3.3V, I
OL
= 10mA)
-
-
0.4
V
V
OH
Output high voltage (VDD = 3.3V, I
OH
= 10mA)
2.5
-
-
V
I
CC
Dynamic supply current normal mode
(3.3V, and 15pF loading)
6.0 7.0 8.3
mA
I
DD
Static supply current standby mode
-
0.6
-
mA
VDD Operating
voltage 3.0
3.3
3.6
V
t
ON
Power up time (first locked clock cycle after power up)
-
0.18
-
mS
Z
OUT
Clock output impedance
-
50
-


July 2005
P2008A
rev 1.3
General purpose EMI Reduction IC
5 of 9
Notice: The information in this document is subject to change without notice.
AC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
f
IN
Input
frequency
4
20
32
MHz
DIV2 =0
2
10
16
f
OUT
Output
frequency
DIV2 =1
4
20
32
MHz
t
LH
*
Output rise time (measured at 0.8V to 2.0V)
0.7
0.9
1.1
nS
t
HL
*
Output fall time (measured at 2.0V to 0.8V)
0.6
0.8
1.0
nS
t
JC
Jitter (cycle to cycle)
-
-
360
pS
t
D
Output duty cycle
45
50
55
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF