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Электронный компонент: P2027A

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October 2003
P2027A

rev E
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
General Purpose EMI Reduction IC

Features
FCC approved method of EMI attenuation
Provides up to 20 dB of EMI suppression
Generates a low EMI spread spectrum clock of
the input frequency
Optimized for 27 MHz operation
Internal loop filter minimizes external
components and board space
3 selectable spread ranges and 2 modulation
rate options
SSON control pin for spread spectrum enable
and disable options
Low cycle-to-cycle jitter
3.3V operating voltage
16 mA output drives
TTL or CMOS compatible outputs
Low power CMOS design
Supports digital camera and other digital video
and imaging applications
Available in 8 pin SOIC and TSSOP

Product Description
The P2027 is a versatile spread spectrum frequency
modulator designed specifically for digital camera
and other digital video and imaging applications. The
P2027 reduces electromagnetic interference (EMI) at
the clock source, which provides system wide
reduction of EMI of all clock dependent signals. The
P2027 allows significant system cost savings by
reducing the number of circuit board layers and
shielding that are traditionally required to pass EMI
regulations.
The P2027 uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all-digital method.
The P2027 modulates the output of a single PLL in
order to "spread" the bandwidth of a synthesized
clock and, more importantly, decreases the peak
amplitudes of its harmonics. This results in
significantly lower system EMI compared to the
typical narrow band signal produced by oscillators
and most frequency generators. Lowering EMI by
increasing a signal's bandwidth is called "spread
spectrum clock generation".

Applications
The P2027 is targeted towards DSC market as well
as other imaging and digital video applications like
DVD and VCD players.

Block Diagram
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P2027A

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General Purpose EMI Reduction IC
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Notice: The information in this document is subject to change without notice.


Pin Configuration

Pin Description
Pin#
Pin Name
Type
Description
1
XIN/CLK
I
Connect to crystal or clock.
2 XOUT I
Crystal
output
3 MRA I
Digital logic input used to select Modulation Rate (see Table 1). This pin
has an internal pull-up resistor.
4
VSS
P
Ground Connection. Connect to system ground.
5 SSON I
Digital logic input used to enable Spread Spectrum function (Active Low).
Spread Spectrum function enable when low. This pin has an internal pull-low
resistor.
6
ModOUT
O
Spread Spectrum Clock Output.
7 SR0 I
Digital logic input used to select Spreading Range (see Table 1). This pin
has an internal pull-up resistor.
8
VDD
P
Connect to +3.3V



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General Purpose EMI Reduction IC
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Notice: The information in this document is subject to change without notice.

Table-1 Modulation and Spreading Selection
MRA
SR0
Spread Range
Modulation Rate
0
0
Reserve
Reserve
0
1
+/- 0.30%
(Fin/10)*34.72 KHz
1
0
+/- 0.20%
(Fin/10)*20.83 KHz
1
1
+/- 0.60%
(Fin/10)*20.83 KHz

Spread Spectrum Selection
Table 1 illustrates the possible spread spectrum options. The optimal setting should minimize system EMI to the
fullest without affecting system performance. The spreading is described as a percentage deviation of the center
frequency (Note: the center frequency is the frequency of the external reference input on CLKIN, Pin 1).
Example: P2027 is designed for DSC and digital video and imaging markets and is optimized for 27 MHz under
minimum deviation settings. Selecting P2027's spread options to MRA=1 and SR0=1 for a 27 MHz input signal
provides a percentage deviation of +/-0.60% (see Table 1) from the reference signal. This results in frequency
on ModOUT being swept from 27.16 MHz to 26.84 MHz at a modulation rate of 56.24 KHz (see Table 1). This
particular example (see the below figure) given here is a new EMI reduction method for DSC applications and is
already gaining popularity among leading manufacturers.
Application Schematic for Digital Still Camera
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General Purpose EMI Reduction IC
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Notice: The information in this document is subject to change without notice.


EMC Software Simulation
By using Alliance Semiconductor's proprietary EMC simulation software EMI-lator, radiated system level EMI
analysis can be made easier to allow a quantitative assessment on Alliance's EMI reduction products. The
simulation engine of this EMC software has already been characterized to correlate with the electrical
characteristics of Alliance EMI reduction IC's. The figure below is an example of the simulation result. Please
visit our web site at
www.alsc.com
for information on how to obtain a free copy and demonstration of EMI-lator.

Simulation Result from EMI-lator
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P2027A

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General Purpose EMI Reduction IC
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Notice: The information in this document is subject to change without notice.

Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
V
DD
, V
IN
Voltage on any pin with respect to GND
-0.5 to + 7.0
V
T
STG
Storage
temperature
-65 to +125
C
T
A
Operating
temperature
0 to +70
C

DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
V
IL
Input Low Voltage
GND 0.3
-
0.8
V
V
IH
Input High Voltage
2.0
-
V
DD
+ 0.3
V
I
IL
Input Low Current (pull-up resistor on inputs FS0, SR0
and MRA)
- -
-35
A
I
IH
Input High Current (pull-down resistor on input SSON)
-
-
35
A
I
XOL
XOUT Output Low Current (@ 0.4V, V
DD
= 3.3V)
-
3
-
mA
I
XOH
XOUT Output High Current (@ 2.5V, V
DD
= 3.3V)
-
3
-
mA
V
OL
Output Low Voltage (V
DD
= 3.3V, I
OL
= 20 mA)
-
-
0.4
V
V
OH
Output High Voltage (V
DD
= 3.3V, I
OH
= 20 mA)
2.5
-
-
V
I
DD
Static Supply Current
-
6.0
-
mA
I
CC
Dynamic Supply Current (3.3V and 15 pF loading)
6.0
7.0
8.3
mA
V
DD
Operating Voltage
2.7
3.3
3.8
V
t
ON
Power Up Time (First locked clock cycle after power up)
0.18
ms
Z
OUT
Clock Output Impedance
50

AC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
f
IN
Input Frequency
10
27
30
MHz
MHz
t
LH
*
Output rise time
(Measured at 0.8V to 2.0V)
0.7 0.9 1.1 ns
t
HL
*
Output fall time
(Measured at 0.8V to 2.0V)
0.6 0.8 1.0 ns
t
JC
Jitter (cycle to cycle)
-
-
360
ps
t
D
Output duty cycle
45
50
55
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF