Altera Corporation
25
a8251
Programmable Communications
Interface
June 1997, ver. 2
Data Sheet
A-DS-A8251-2
Features
s
a8251
MegaCore function that provides an interface between a
microprocessor and a serial communication channel
s
Optimized for FLEX
architecture
s
Programmable word length, stop bits, and parity
s
Offers divide-by-1, -16, or -64 mode
s
Supports synchronous and asynchronous operation
s
Uses approximately 528 FLEX logic elements (LEs)
s
Includes:
Error detection
False start bit detection
Automatic break detection
Internal and external sync character detection
s
Functionally based on the Intel M8251A device, except as noted in the
"Variations & Clarifications" on page 44
General
Description
The
a8251
MegaCore function provides an interface between a
microprocessor and a serial communications channel. The
a8251
receives
and transmits data in a variety of configurations including 7- or 8-bit data
words, with odd, even, or no parity, and 1 or 2 stop bits. The transmitter
and receiver can be designed for synchronous or asynchronous operation.
See
Figure 1
.
Figure 1. a8251 Symbol
CLK
CnD
DIN[7..0]
EXTSYNCD
nCS
nCTS
nDSR
nRD
nRXC
nTXC
nWR
RESET
RXD
A8251
DOUT[7..0]
nDTR
nEN
nRTS
RXRDY
SYN_BRK
TXD
TXEMPTY
TXRDY
26
Altera Corporation
a8251 Programmable Communications Interface Data Sheet
Table 1
describes input and output ports of the
a8251
.
Table 1. a8251 Ports (Part 1 of 2)
Name
Type
Polarity
Description
clk
Input
Master clock input.
cnd
Input
Control/data select. When the
cnd
signal goes high, the microprocessor
selects status/control data to read/write; otherwise, the microprocessor
selects receiver/transmitter data to read/write.
din[7..0]
Input
Parallel data input from the microprocessor or other controlling device.
extsyncd
Input
High
External sync detect. In synchronous designs, when the
extsyncd
signal
is asserted, the
a8251
begins receiving data on the next rising edge of the
nrxc
signal.
ncs
Input
Low
Chip select from the microprocessor. When the
ncs
signal is asserted, all
read or write operations are enabled.
ncts
Input
Low
Clear to send, typically a modem signal name. When the
ncts
signal is
asserted, and if the
txen
bit of the command instruction register is set, data
transmission is enabled.
ndsr
Input
Low
Data set ready, typically a modem signal name. The state of this input may
be tested by reading status register bit 7 (
dsr
).
nrd
Input
Low
Read control for the registers. When the
nrd
and the
ncs
signals are both
low, the microprocessor reads from the registers.
nrxc
Input
Low
Receive clock. The receiver control logic samples the
nrxd
based on the
state of the
nrxc
signal and the baud rate factor bits in the mode instuction
register.
ntxc
Input
Low
Transmit clock. Data is asserted to the
txd
on the falling edge of
ntxc
.
nwr
Input
Low
Write control for the registers. When the
nwr
and the
ncs
signals are both
low, the microprocessor writes to the registers.
nreset
Input
Low
Asynchronous reset for the registers and control logic.
rxd
Input
Receive data. Serial input from the modem or peripheral.
dout[7..0]
Output
Low
Parallel data output to the microprocessor or other controlling device.
ndtr
Output
Low
Data terminal ready, typically a modem signal name. Bit 1 of the command
instruction register sets the
ndtr
signal.
nen
Output
Low
Output enable for the output data bus. When the
nen
signal is asserted, the
output data is enabled on the
dout[7..0]
bus line.
nrts
Output
Low
Request to send, typically a modem signal name. Bit 5 of the command
instruction register sets the
nrts
signal.
rxrdy
Output
High
Receiver ready. A high
rxrdy
signal indicates that the
a8251
has received
a character to be read by the microprocessor.
syn_brk
Output
High
Sync/break detect. In synchronous operation, when the
extsyncd
signal
is asserted, the
a8251
begins receiving data on the next rising edge of the
nrxc
signal. In asynchronous operation,
syn_brk
indicates a break
condition on
rxd
.
Altera Corporation
27
a8251 Programmable Communications Interface Data Sheet
Functional
Description
Figure 2
shows the
a8251
block diagram.
Figure 2. a8251 Block Diagram
Name
Type
Polarity
Description
txd
Output
Transmit data. Serial output to modem or peripheral.
txempty
Output
High
Transmitter empty. Indicates that the transmitter logic has no more data to
send.
txrdy
Output
High
Transmitter ready. When the
txrdy
signal is asserted, the transmitter logic
is ready to receive another data byte. This output is conditional upon the
state of the
cts
input and the
txen
command bit.
Table 1. a8251 Ports (Part 2 of 2)
nrd
nwr
cnd
din[7..0]
dout[7..0]
Read/Write
Control Logic &
Registers
Transmitter
Logic
ntxc
txempty
txrdy
txd
ncs
Modem
Control
nrts
ncts
ndtr
ndsr
Receiver
Logic
rxd
extsyncd
syn_brk
nrxc
rxrdy
reset
clk
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Altera Corporation
a8251 Programmable Communications Interface Data Sheet
The
a8251
contains the following registers:
s
Mode instruction
s
Command instruction
s
Status
s
Sync character one
s
Sync character two
s
Transmitter buffer
s
Receiver buffer
Mode Instruction Register
The mode instruction register (MIR) supports both synchronous and
asynchronous operation.
Bits 0 and 1 of the MIR are the baud rate factor bits and determine the ratio
between the data rate and the clocks. If bits 0 and 1 are set to a logic low,
then the
a8251
is programmed for synchronous operation; otherwise, the
a8251
operates asynchronously.
Asynchronous Operation
When the
a8251
is programmed for asynchronous operation, the MIR
contains the bits shown in
Table 2
.
Table 2. Mode Instruction Register Bits (Asynchronous Operation)
Data Bit
Signal Name
0
Baud rate factor (
b1
)
1
Baud rate factor (
b2
)
2
Word length select (
l1
)
3
Word length select (
l2
)
4
Parity select (
pen
)
5
Parity select (
ep
)
6
Stop bit select (
s1
)
7
Stop bit select (
s2
)
Altera Corporation
29
a8251 Programmable Communications Interface Data Sheet
Baud Rate Factor
Bits 0 and 1 (
b1
,
b2
) of the MIR are the baud rate factor bits, which
determine the ratio between the data rate and the clocks. The ratios are
identical when transmitting and receiving. The baud rate factor bits also
provide a means of programming the
a8251
for synchronous operation.
Table 3
shows the logic level of the baud rate factor bits and the
corresponding programmed function.
Word Length Select
Bits 2 and 3 (
l1
,
l2
) of the MIR are the word length select bits, which are
used to select the character length of the data byte.
Table 4
shows the logic
level of the word length select bits and the corresponding word length.
Table 3. Baud Rate Factor Bits
b2 b1
Programmed
Function
0
0
Synchronous operation.
0
1
Divide-by-1 mode. Clock and data rates are identical. External
logic is responsible for synchronizing the
rxd
signal to the
nrxc
signal. The
rxd
signal is sampled on the rising edge of
the
nrxc
signal, and the
txd
signal is asserted on the falling
edge of the
ntxc
signal.
1
0
Divide-by-16 mode. The clock rate is 16 times the data rate.
After start bit detection (
rxd
low), the
rxd
signal is sampled on
the ninth rising edge of
nrxc
. After writing to the transmitter
register, the
txd
signal is asserted on the first falling edge of
the
ntxc
signal and every 16 clocks thereafter.
1
1
Divide-by-64 mode. The clock rate is 64 times the data rate.
After start bit detection (
rxd
low), the
rxd
signal is sampled on
the 33rd rising edge of the
nrxc
. After writing to the transmitter
register (assuming the transmission is enabled),
txd
is
asserted on the first falling edge of the
ntxc
signal and every
64 clocks thereafter.
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