C8237

Programmable
DMA Controller
Altera Core

The C8237 Programmable DMA Controller core (C8237 core) is a peripheral inter-
face circuit for microprocessor systems. The core is designed for use with an
external, 8-bit address latch. It contains four independent channels and may be ex-
panded to any number or channels by cascading additional controller chips. Each
channel has a full 64K address and word count capability.

Applications

The C8237 core is designed to improve system performance by allowing external
devices to directly transfer information from the system memory.

Block Diagram

Enable/Disable control of indi-
vidual DMA requests
Four, independent DMA chan-
nels
Independent auto-initialization of
all channels
Memory-to-Memory transfers
Memory block initialization
Address increment of decrement
Directly expandable to any
number of channels
End of process input for termi-
nating transfers
Software DMA requests
Independent polarity control for
DREQ and DACK signals
The C8237 was developed in
HDL and synthesizes to ap-
proximately 5,500 gates
depending on the technology
used.
Functionality based on the Intel
8237

RESET

Timing

and

Control

CLK

CSN

AEN

READY

State

Machine

HLDA

16 Bit

Decrementor

Temp Word

Count Reg

16 Bit

Incrementor/
Decrementor

Temp Address Reg

C8237REG

Fixed

Priority

and

Rotating

Priority

Logic

DREQ(3:0)

HRQ

DACK(3:0)

Command

Register

Mask

Register

Request

Register

Mode

Register

Status

Register

Temporary

Register

DBIN(7:0)

AIN[3:0]

AOUT[7:0]

EOPNOUT

MEMRN

ADSTB

MEMWN

IOWNOUT

IORNOUT

IORNIN

IOWNIN

EOPNIN

DBOUT(7:0)

Channel-0

Current Word

Count Register

Current Word

Address Register

Base Word Count

Register

Base Word Address

Register

Write

Read/Write

Channel-1

Channel-2

Channel-3

March 2004

Bit4: 0 -> Fixed priority

Functional Description

1 -> Rotating priority

The C8237 core is partitioned into modules as shown in the
block diagram and described below:

Bit5: 0 -> Late write

1 -> Extended write

Timing & Control

X -> if bit3 = 1

It generates internal timing and external control signals for the
C8237. The timing Control block derives internal timing from
the clock input. The C8237 operates in two major cycles, idle
cycle (Si) and Active cycle (S0, S1, S2, S3, and S4). Memory-
to-memory transfers require a read-from and a write-to-
memory to complete each transfer. It requires eight states for
a single transfer. The first four states (S11, S12, S13, S14)
are used for the read-from 璵emory half and the last four
states (S21, S22, S23, S24) for the write-to-memory half of
the transfer. Each state is composed of one full clock period.

Bit6: 0 -> DREQ sense active high
1 -> DREQ sense active low
Bit7: 0 -> DACK sense active low
1 -> DACK sense active high
Mode Register
Write Mode Register Command:

A3 A2 A1 A0 IORN IOWN

1 0 1 1 1

Fixed Priority & Rotating Priority Logic

Each channel has a 6-bit Mode register. It is programmed by
the microprocessor.

The Fixed Priority fixes the channels in priority order based
upon the descending value of their number. The lowest prior-
ity channel is 3 and the highest priority channel is 0.

With Rotating Priority, the last channel to get service be-
comes the lowest priority channel with the others rotating
accordingly.

D7 D6 D5 D4 D3 D2 D1 D0

Bit1 & Bit0: 00 -> Channel 0
01 -> Channel 1

C8237 Registers

10 -> Channel 2

The C8237 contains 344 bits of internal memory in the form
of registers. CSN must be low when the microprocessor is at-
tempting to write or read the internal registers of the C8237.

11 -> Channel 3
Bit3 & Bit2: 00 -> Verify transfer (pseudo transfer)

Command Register

01 -> Write transfer (from I/O to the memory)

Write Command Register Command:

10 -> Read transfer (from the memory to I/O)

A3 A2 A1 A0 IORN IOWN

1 0 0 0 1

11 -> Illegal
XX -> if bits 6 and 7 = 11

This 8-bit register controls the operation of the C8237. It is
programmed by the microprocessor and is cleared by Reset
or a Master Clear instruction.

Bit4: 0 -> Auto initialization disable
1 -> Auto initialization enable

Bit5: 0 -> Address increment select

D7 D6 D5 D4 D3 D2 D1 D0

1 -> Address decrement select

Bit0: 0 -> Memory-to-memory disable

Bit7 & Bit6: 00 -> Demand mode

1 -> Memory-to-memory enable

01 -> Single mode

Bit1: 0 -> Channel 0 address hold disable

10 -> Block mode

1 -> Channel 0 address hold enable

11 -> Cascade mode

X -> if bit0 = 0

Demand Transfer Mode: The device will continue making
transfers until a TC or external EOPN is encountered or until
DREQ goes inactive.

Bit2: 0 -> Controller enable
1 -> Controller disable
Bit3: 0 -> Normal timing

Single Transfer Mode: The device makes one transfer only.
DREQ must be held active until DACK becomes active in or-
der to be recognized.

1 -> Compressed timing
X -> if bit 0 = 1

Block Transfer Mode: The device is active by DREQ or
software request to continue making transfers during the ser-
vice until a TC or an external EOPN is encountered. DREQ
need only be held active until DACK becomes active.
Cascade Transfer Mode: This mode is used to cascade
more than one C8237 together for simple system expansion.
The ready input is ignored in this cascade transfer mode.

Cast, Inc.

Programming Single Mask Register Bits:

Request Register
Write Request Register Command:

Write Single Mask Register Bit Command:

A3 A2 A1 A0 IORN IOWN

1 0 0 1 1

A3 A2 A1 A0 IORN IOWN

1 0 1 0 1

Each channel has a request bit associated with it in the 4-bit
Request register. These are non-maskable and subject to pri-
oritization by the Priority Encoder. Each register bit is set or
reset separately under software control or is cleared upon
generation of a TC or external EOPN. The entire register is
cleared by a Reset. In order to make a software request, the
channel must be in Block Mode.

X X X X D3 D2 D1 D0

Bit0: 0 -> Clear channel 0 mask bit
1 -> Set channel 0 mask bit
Bit1: 0 -> Clear channel 1 mask bit
1 -> Set channel 1 mask bit

X X X X X D2 D1 D0

Bit2: 0 -> Clear channel 2-mask bit

Bit1 & Bit0: 00 -> Channel 0

1 -> Set channel 2 mask bit

01 -> Channel 1

Bit3: 0 -> Clear channel 3-mask bit

10 -> Channel 2

1 -> Set channel 3 mask bit

11 -> Channel 3

Status Register

Bit2: 0 -> Reset request bit

Read Status Register Command:

1 -> Set request bit

A3 A2 A1 A0 IORN IOWN

1 0 0 0 0

Mask Register
Each channel has a mask bit associated with it which can be
set to disable the incoming DREQ. Each mask bit is set when
its associated channel produces an EOPN if the channel is
not programmed for Auto initialize. Each bit of the 4-bit Mask
register may also be set or cleared separately under software
control. The entire register is also set by a Reset. This dis-
ables all DMA requests until a clear Mask register instruction
allows them to occur.

This register is available to be read out of the C8237 by the
microprocessor. It contains information about the status of the
devices at this point. Bits 0-3 are set when that channel
reaches a TC or an external EOPN is applied. These bits are
cleared upon Reset and on each Status Read. Bits 4-7 are
set whenever their corresponding channel is requesting.

D7 D6 D5 D4 D3 D2 D1 D0

Programming All Mask Register Bits:

Bit0: 1 -> Channel 0 has reached TC

Write All Mask Register Bits Command:

Bit1: 1 -> Channel 1 has reached TC

A3 A2 A1 A0 IORN IOWN

1 1 1 1 1

Bit2: 1 -> Channel 2 has reached TC
Bit3: 1 -> Channel 3 has reached TC

Bit4: 1 -> Channel 0 request

X X X X X D2 D1 D0

Bit5: 1 -> Channel 1 request

Bit1 & Bit0: 00 -> Channel 0

Bit6: 1 -> Channel 2 request

01 -> Channel 1

Bit7: 1 -> Channel 3 request

10 -> Channel 2

11 -> Channel 3
Bit2: 0 -> Clear mask bit
1 -> Set mask bit

Cast, Inc.

Word Count and Address Register Command Codes

Temporary Register
Read Temporary Register Command:

Write -> CSN = 0, IORN = 1 and IOWN = 0

A3 A2 A1 A0 IORN IOWN

1 1 0 1 0

Read -> CSN = 0, IORN = 0 and IOWN = 1

A3 A2 A1 A0 FF DB0-DB7

0 A0-A7

CH 0
Base and
Current Address

0 0 0 0 1 A8-A15

0 W0-W7

CH 0
Base and Cur-
rent Word Count

0 0 0 1 1 W8-W15

0 A0-A7

CH 1
Base and
Current Address

0 0 1 0 1 A8-A15

0 W0-W7

CH 1
Base and Cur-
rent Word Count

0 0 1 1 1 W8-W15

0 A0-A7

CH 2
Base and
Current Address

0 1 0 0 1 A8-A15

0 W0-W7

CH 2
Base and Cur-
rent Word Count

0 1 0 1 1 W8-W15

0 A0-A7

CH 3
Base and
Current Address

0 1 1 0 1 A8-A15

0 W0-W7

CH 3
Base and Cur-
rent Word Count

0 1 1 1 1 W8-W15

This register is used to hold data during memory-to-memory
transfers. Following the completion of the transfers, the last
word moved can be read by the microprocessor. The tempo-
rary register is cleared by a Reset.

Current Address Register
Each channel has a 16-bit Current Address register. This reg-
ister holds the value of the address used during DMA
transfers. The address is automatically incremented or dec-
remented after each transfer and the intermediate values of
the address are stored in the Current Address register during
the transfer. This register is written or read by the microproc-
essor.

Current Word Register
Each channel has a 16-bit Current Word Count register. This
register determines the number of transfers to be performed.
The word count is decremented after each transfer. When the
value in the register goes from zero to FFFFH, a TC will be
generated. This register is loaded or read by the microproc-
essor in the Program Condition.

Software Commands

These three commands do not depend on any specific bit
pattern on the data bus.

Base Address and Base Word Count Registers
Each channel has a 16-bit Base Address and 16-bit Base
Word Count register. These registers store the original value,
which will be loaded to current registers during Auto initialize.

Clear First/Last Flip-Flop Command:

A3 A2 A1 A0 IORN IOWN

1 1 0 0 1

This command must be executed prior to writing or reading
new address or word count information to the C8237.
Master Clear Command:

A3 A2 A1 A0 IORN IOWN

1 1 0 1 1

This command has the same effect as the hardware Reset.
The Command, Status, Request, Temporary, and Internal
First/Last Flip-Flop registers are cleared and the Mask regis-
ter is set. The C8237 will be in the idle cycle.

Clear Mask Register Command:

A3 A2 A1 A0 IORN IOWN

1 1 1 0 1

This command clears the mask bits of all four channels, ena-
bling them to accept DMA requests

Cast, Inc.

Temporary Word Count Register (16 Bit Decrementor)
It will decrement the word count after each transfer. When the
value in the register goes from zero to FFFFH, a Terminal
Count (TC) will be generated.
Temporary Address Register (16 Bit Incremen-
tor/Decrementor)
Base on the mode of the address, the address will be decre-
mented or incremented after each transfer. And the
intermediate values of the address are stored in the Current
Address register during the transfer.

Implementation Results

The following are typical performance and utilization results us-
ing a variety of Altera devices.

Supported

Device

Utilization

Performance

Family

Tested

LEs

Memory

bits

max

Cyclone EP1C20-6

1,007

0 0 97

MHz

Stratix EP1S20-5

1,007

0 0 94

MHz

Stratix-II EP2S60-3 816

140

MHz

Support

The core as delivered is warranted against defects for three
years from purchase. Thirty days of phone and email technical
support are included, starting with the first interaction. Addi-
tional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and
rigorous code coverage measurements.

Deliverables

The core includes everything required for successful implemen-
tation:
Encrypted Licenses

� Post-synthesis EDIF netlist
� Assignment & Configuration
� Symbol file
� Include file
� Wrapper for matching the I/O of the original device
� Vectors for testbench

HDL Source Licenses

� VHDL or Verilog RTL source code
� Testbench
� Wrapper for matching the I/O of the original device
� Vectors for testbench
� Expected results for testbench
� Simulation and synthesis script

Contents subject to change without notice. July 2003

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: C8237

Document Outline

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: C8237

Document Outline

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: C8237