Document Outline
- APEX 20KC Programmable Logic Device Data Sheet
Altera Corporation
1
APEX 20KC
Programmable Logic
Device
April 2002 ver. 2.1
Data Sheet
DS-APEX20KC-2.1
Features...
Programmable logic device (PLD) manufactured using a 0.15-
m all-
layer copper-metal fabrication process
25 to 35% faster design performance than APEX
TM
20KE devices
Pin-compatible with APEX 20KE devices
High-performance, low-power copper interconnect
MultiCore
TM
architecture integrating look-up table (LUT) logic
and embedded memory
LUT logic used for register-intensive functions
Embedded system blocks (ESBs) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
High-density architecture
200,000 to 1 million typical gates (see
Table 1
)
Up to 38,400 logic elements (LEs)
Up to 327,680 RAM bits that can be used without reducing
available logic
Notes to
Table 1
:
(1)
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
(2)
PLL: phase-locked loop.
(3)
The -7 speed grade provides the fastest performance.
Table 1. APEX 20KC Device Features
Note (1)
Feature
EP20K200C
EP20K400C
EP20K600C
EP20K1000C
Maximum system gates
526,000
1,052,000
1,537,000
1,772,000
Typical gates
200,000
400,000
600,000
1,000,000
LEs
8,320
16,640
24,320
38,400
ESBs
52
104
152
160
Maximum RAM bits
106,496
212,992
311,296
327,680
PLLs
(2)
2
4
4
4
Speed grades
(3)
-7, -8, -9
-7, -8, -9
-7, -8, -9
-7, -8, -9
Maximum macrocells
832
1,664
2,432
2,560
Maximum user I/O pins
376
488
588
708
2
Altera Corporation
APEX 20KC Programmable Logic Device Data Sheet
...and More
Features
Low-power operation design
1.8-V supply voltage (see
Table 2
)
Copper interconnect reduces power consumption
MultiVolt
TM
I/O support for 1.8-V, 2.5-V, and 3.3-V
interfaces
ESBs offering programmable power-saving mode
Flexible clock management circuitry with up to four phase-
locked loops (PLLs)
Built-in low-skew clock tree
Up to eight global clock signals
ClockLock
TM
feature reducing clock delay and skew
ClockBoost
TM
feature providing clock multiplication and
division
ClockShift
TM
feature providing programmable clock phase
and delay shifting
Powerful I/O features
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2
for 3.3-V operation at 33 or 66 MHz and 32 or
64 bits
Support for high-speed external memories, including DDR
synchronous dynamic RAM (SDRAM) and ZBT static RAM
(SRAM)
16 input and 16 output LVDS channels at 840 megabits per
second (Mbps)
Direct connection from I/O pins to local interconnect
providing fast t
CO
and t
SU
times for complex logic
MultiVolt I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces
Programmable clamp to V
CCIO
Individual tri-state output enable control for each pin
Programmable output slew-rate control to reduce
switching noise
Support for advanced I/O standards, including low-
voltage differential signaling (LVDS), LVPECL, PCI-X,
AGP, CTT, SSTL-3 and SSTL-2, GTL+, and HSTL Class I
Supports hot-socketing operation
Pull-up on I/O pins before and during configuration
Note to
Table 2
:
(1)
APEX 20KC devices can be 5.0-V tolerant by using an external resistor.
Table 2. APEX 20KC Supply Voltages
Feature
Voltage
Internal supply voltage (V
CCINT
)
1.8 V
MultiVolt I/O interface voltage levels (V
CCIO
) 1.8 V, 2.5 V, 3.3 V, 5.0 V
(1)
Altera Corporation
3
APEX 20KC Programmable Logic Device Data Sheet
Advanced interconnect structure
Copper interconnect for high performance
Four-level hierarchical FastTrack
interconnect structure
providing fast, predictable interconnect delays
Dedicated carry chain that implements arithmetic functions
such as fast adders, counters, and comparators
(automatically used by software tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software
tools and megafunctions)
Interleaved local interconnect allows one LE to drive 29
other LEs through the fast local interconnect
Advanced software support
Software design support and automatic place-and-route
provided by the Altera
Quartus
TM
II development system
for Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
Altera MegaCore
functions and Altera Megafunction
Partners Program (AMPP
SM
) megafunctions optimized for
APEX 20KC architecture available
NativeLink
TM
integration with popular synthesis,
simulation, and timing analysis tools
Quartus II SignalTap
embedded logic analyzer simplifies
in-system design evaluation by giving access to internal
nodes during device operation
Supports popular revision-control software packages
including PVCS, RCS, and SCCS
Table 3. APEX 20KC QFP & BGA Package Options & I/O Count
Notes (1)
,
(2)
Device
208-Pin PQFP 240-Pin PQFP
356-Pin BGA
652-Pin BGA
EP20K200C
136
168
271
EP20K400C
488
EP20K600C
488
EP20K1000C
488
4
Altera Corporation
APEX 20KC Programmable Logic Device Data Sheet
Notes to
Tables 3
and
4
:
(1)
I/O counts include dedicated input and clock pins.
(2)
APEX 20KC device package types include plastic quad flat pack (PQFP),
1.27-mm pitch ball-grid array (BGA), and 1.00-mm pitch FineLine BGA
TM
packages.
(3)
This device uses a thermally enhanced package, which is taller than the
regular package. Consult the
Altera Device Package Information Data Sheet
for
detailed package size information.
Table 4. APEX 20KC FineLine BGA Package Options & I/O Count
Notes (1)
,
(2)
Device
484 Pin
672 Pin
1,020 Pin
EP20K200C
376
EP20K400C
488
(3)
EP20K600C
508
(3)
588
EP20K1000C
508
(3)
708
Table 5. APEX 20KC QFP & BGA Package Sizes
Feature
208-Pin PQFP
240-Pin PQFP
356-Pin BGA
652-Pin BGA
Pitch (mm)
0.50
0.50
1.27
1.27
Area (mm
2
)
924
1,218
1,225
2,025
Length
Width (mm
mm)
30.4
30.4
34.9
34.9
35.0
35.0
45.0
45.0
Table 6. APEX 20KC FineLine BGA Package Sizes
Feature
484 Pin
672 Pin
1,020 Pin
Pitch (mm)
1.00
1.00
1.00
Area (mm
2
)
529
729
1,089
Length
Width (mm
mm)
23
23
27
27
33
33
Altera Corporation
5
APEX 20KC Programmable Logic Device Data Sheet
General
Description
Similar to APEX 20K and APEX 20KE devices, APEX 20KC devices offer
the MultiCore architecture, which combines the strengths of LUT-based
and product-term-based devices with an enhanced memory structure.
LUT-based logic provides optimized performance and efficiency for data-
path, register-intensive, mathematical, or digital signal processing (DSP)
designs. Product-term-based logic is optimized for complex
combinatorial paths, such as complex state machines. LUT- and product-
term-based logic combined with memory functions and a wide variety of
MegaCore and AMPP functions make the APEX 20KC architecture
uniquely suited for SOPC designs. Applications historically requiring a
combination of LUT-, product-term-, and memory-based devices can now
be integrated into one APEX 20KC device.
APEX 20KC devices include additional features such as enhanced I/O
standard support, CAM, additional global clocks, and enhanced
ClockLock clock circuitry.
Table 7
shows the features included in
APEX 20KC devices.
Table 7. APEX 20KC Device Features (Part 1 of 2)
Feature
APEX 20KC Devices
MultiCore system integration
Full support
Hot-socketing support
Full support
SignalTap logic analysis
Full support
32-/64-bit, 33-MHz PCI
Full compliance
32-/64-bit, 66-MHz PCI
Full compliance in -7 and -8 speed grades in
selected devices
MultiVolt I/O
1.8-V, 2.5-V, or 3.3-V V
CCIO
V
CCIO
selected bank by bank
5.0-V tolerant with use of external resistor
ClockLock support
Clock delay reduction
m /(n
v) clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift circuitry
LVDS support
Up to four PLLs
ClockShift clock phase adjustment
Dedicated clock and input pins
Eight
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