Document Outline
- FLEX 10KE Embedded Programmable Logic Device Data Sheet
Altera Corporation
1
FLEX 10KE
Embedded Programmable
Logic Device
January 2003, ver. 2.5
Data Sheet
DS-F10KE-2.5
Features...
Embedded programmable logic devices (PLDs), providing
system-on-a-programmable-chip (SOPC) integration in a single
device
Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
Dual-port capability with up to 16-bit width per embedded array
block (EAB)
Logic array for general logic functions
High density
30,000 to 200,000 typical gates (see
Tables 1
and
2
)
Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be
used without reducing logic capacity
System-level features
MultiVolt
TM
I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
Low power consumption
Bidirectional I/O performance (t
SU
and t
CO
) up to 212 MHz
Fully compliant with the PCI Special Interest Group (PCI SIG)
PCI Local Bus Specification, Revision 2.2
for 3.3-V operation at
33 MHz or 66 MHz
-1 speed grade devices are compliant with
PCI Local Bus
Specification, Revision 2.2
, for 5.0-V operation
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic
f
For information on 5.0-V FLEX
10K or 3.3-V FLEX 10KA devices, see the
FLEX 10K Embedded Programmable Logic Family Data Sheet
.
Table 1. FLEX 10KE Device Features
Feature
EPF10K30E
EPF10K50E
EPF10K50S
Typical gates
(1)
30,000
50,000
Maximum system gates
119,000
199,000
Logic elements (LEs)
1,728
2,880
EABs
6
10
Total RAM bits
24,576
40,960
Maximum user I/O pins
220
254
2
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Note to tables:
(1)
The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum
system gates.
(2)
New EPF10K100B designs should use EPF10K100E devices.
...and More
Features
Fabricated on an advanced process and operate with a 2.5-V
internal supply voltage
In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
ClockLock
TM
and ClockBoost
TM
options for reduced clock
delay/skew and clock multiplication
Built-in low-skew clock distribution trees
100% functional testing of all devices; test vectors or scan chains
are not required
Pull-up on I/O pins before and during configuration
Flexible interconnect
FastTrack
Interconnect continuous routing structure for fast,
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Tri-state emulation that implements internal tri-state buses
Up to six global clock signals and four global clear signals
Powerful I/O pins
Individual tri-state output enable control for each pin
Open-drain option on each I/O pin
Programmable output slew-rate control to reduce switching
noise
Clamp to V
CCIO
user-selectable on a pin-by-pin basis
Supports hot-socketing
Table 2. FLEX 10KE Device Features
Feature
EPF10K100E
(2)
EPF10K130E
EPF10K200E
EPF10K200S
Typical gates
(1)
100,000
130,000
200,000
Maximum system gates
257,000
342,000
513,000
Logic elements (LEs)
4,992
6,656
9,984
EABs
12
16
24
Total RAM bits
49,152
65,536
98,304
Maximum user I/O pins
338
413
470
Altera Corporation
3
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Software design support and automatic place-and-route provided by
Altera's development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800
Flexible package options
Available in a variety of packages with 144 to 672 pins, including
the innovative FineLine BGA
TM
packages (see
Tables 3
and
4
)
SameFrame
TM
pin-out compatibility between FLEX 10KA and
FLEX 10KE devices across a range of device densities and pin
counts
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
DesignWare components, Verilog HDL, VHDL, and other interfaces
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,
VeriBest, and Viewlogic
Notes:
(1)
FLEX 10KE device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), pin-grid array (PGA), and ball-grid array (BGA) packages.
(2)
Devices in the same package are pin-compatible, although some devices have more I/O pins than others. When
planning device migration, use the I/O pins that are common to all devices.
(3)
This option is supported with a 484-pin FineLine BGA package. By using SameFrame pin migration, all
FineLine BGA packages are pin-compatible. For example, a board can be designed to support 256-pin, 484-pin, and
672-pin FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration
is set.
Table 3. FLEX 10KE Package Options & I/O Pin Count
Notes (1)
,
(2)
Device
144-Pin
TQFP
208-Pin
PQFP
240-Pin
PQFP
RQFP
256-Pin
FineLine
BGA
356-Pin
BGA
484-Pin
FineLine
BGA
599-Pin
PGA
600-Pin
BGA
672-Pin
FineLine
BGA
EPF10K30E
102
147
176
220
220
(3)
EPF10K50E
102
147
189
191
254
254
(3)
EPF10K50S
102
147
189
191
220
254
254
(3)
EPF10K100E
147
189
191
274
338
338
(3)
EPF10K130E
186
274
369
424
413
EPF10K200E
470
470
470
EPF10K200S
182
274
369
470
470
470
4
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
General
Description
Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices.
Based on reconfigurable CMOS SRAM elements, the FLEX architecture
incorporates all features necessary to implement common gate array
megafunctions. With up to 200,000 typical gates, FLEX 10KE devices
provide the density, speed, and features to integrate entire systems,
including multiple 32-bit buses, into a single device.
The ability to reconfigure FLEX 10KE devices enables 100
%
testing prior
to shipment and allows the designer to focus on simulation and design
verification. FLEX 10KE reconfigurability eliminates inventory
management for gate array designs and generation of test vectors for fault
coverage.
Table 5
shows FLEX 10KE performance for some common designs. All
performance values were obtained with Synopsys DesignWare or LPM
functions. Special design techniques are not required to implement the
applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Table 4. FLEX 10KE Package Sizes
Device
144-
Pin
TQFP
208-Pin
PQFP
240-Pin
PQFP
RQFP
256-Pin
FineLine
BGA
356-
Pin
BGA
484-Pin
FineLine
BGA
599-Pin
PGA
600-
Pin
BGA
672-Pin
FineLine
BGA
Pitch (mm)
0.50
0.50
0.50
1.0
1.27
1.0
1.27
1.0
Area (mm
2
)
484
936
1,197
289
1,225
529
3,904
2,025
729
Length
width
(mm
mm)
22
22 30.6
30.6 34.6
34.6
17
17
35
35
23
23
62.5
62.5 45
45
27
27
Altera Corporation
5
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Notes:
(1)
This application uses combinatorial inputs and outputs.
(2)
This application uses registered inputs and outputs.
Table 6
shows FLEX 10KE performance for more complex designs. These
designs are available as Altera MegaCore
functions.
Note:
(1)
These values are for calculation time. Calculation time = number of clocks required/f
max
. Number of clocks
required = ceiling [log 2 (points)/2]
[points +14 + ceiling]
Table 5. FLEX 10KE Performance
Application
Resources Used
Performance
Units
LEs
EABs
-1 Speed Grade -2 Speed Grade -3 Speed Grade
16-bit loadable counter
16
0
285
250
200
MHz
16-bit accumulator
16
0
285
250
200
MHz
16-to-1 multiplexer
(1)
10
0
3.5
4.9
7.0
ns
16-bit multiplier with 3-stage
pipeline
(2)
592
0
156
131
93
MHz
256
16 RAM read cycle
speed
(2)
0
1
196
154
118
MHz
256
16 RAM write cycle
speed
(2)
0
1
185
143
106
MHz
Table 6. FLEX 10KE Performance for Complex Designs
Application
LEs Used
Performance
Units
-1 Speed Grade -2 Speed Grade -3 Speed Grade
8-bit, 16-tap parallel finite impulse
response (FIR) filter
597
192
156
116
MSPS
8-bit, 512-point fast Fourier
transform (FFT) function
1,854
23.4
28.7
38.9
s
(1)
113
92
68
MHz
a16450
universal asynchronous
receiver/transmitter (UART)
342
36
28
20.5 MHz
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