Document Outline
- MAX 3000A Programmable Logic Device Family Data Sheet
Altera Corporation
1
MAX 3000A
Programmable Logic
Device Family
December 2002, ver. 3.2
Data Sheet
DS-MAX3000A-3.2
Features...
Highperformance, lowcost CMOS EEPROMbased programmable
logic devices (PLDs) built on a MAX
architecture (see
Table 1
)
3.3-V in-system programmability (ISP) through the builtin
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
ISP circuitry compliant with IEEE Std. 1532
Builtin boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
Enhanced ISP features:
Enhanced ISP algorithm for faster programming
ISP_Done bit to ensure complete programming
Pull-up resistor on I/O pins during insystem programming
Highdensity PLDs ranging from 600 to 10,000 usable gates
4.5ns pintopin logic delays with counter frequencies of up to
227.3 MHz
MultiVolt
TM
I/O interface enabling the device core to run at 3.3 V,
while I/O pins are compatible with 5.0V, 3.3V, and 2.5V logic
levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), plastic Jlead chip carrier
(PLCC), and FineLine BGA
TM
packages
Hotsocketing support
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
Table 1. MAX 3000A Device Features
Feature
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
Usable gates
600
1,250
2,500
5,000
10,000
Macrocells
32
64
128
256
512
Logic array blocks
2
4
8
16
32
Maximum user I/O
pins
34
66
96
158
208
t
PD
(ns)
4.5
4.5
5.0
7.5
7.5
t
SU
(ns)
2.9
2.8
3.3
5.2
5.6
t
CO1
(ns)
3.0
3.1
3.4
4.8
4.7
f
CNT
(MHz)
227.3
222.2
192.3
126.6
116.3
2
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
...and More
Features
PCI compatible
Busfriendly architecture including programmable slewrate control
Opendrain output option
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
Programmable powersaving mode for a power reduction of over
50% in each macrocell
Configurable expander productterm distribution, allowing up to
32 product terms per macrocell
Programmable security bit for protection of proprietary designs
Enhanced architectural features, including:
6 or 10 pin or logicdriven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Programmable output slewrate control
Software design support and automatic placeandroute provided
by Altera's development systems for Windowsbased PCs and Sun
SPARCstations, and HP 9000 Series 700/800 workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
thirdparty manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
Programming support with the Altera master programming unit
(MPU), MasterBlaster
TM
communications cable, ByteBlasterMV
TM
parallel port download cable, BitBlaster
TM
serial download cable as
well as programming hardware from thirdparty manufacturers and
any incircuit tester that supports Jam
TM
Standard Test and
Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code
Files (.jbc), or Serial Vector Format Files (.svf)
General
Description
MAX 3000A devices are lowcost, highperformance devices based on the
Altera MAX architecture. Fabricated with advanced CMOS technology,
the EEPROMbased MAX 3000A devices operate with a 3.3-V supply
voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as
fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices
in the 4, 5, 6, 7, and 10 speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2
. See
Table 2
.
Altera Corporation
3
MAX 3000A Programmable Logic Device Family Data Sheet
The MAX 3000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and highdensity small-scale integration (SSI),
medium-scale integration (MSI), and large-scale integration (LSI) logic
functions. The MAX 3000A architecture easily integrates multiple devices
ranging from PALs, GALs, and 22V10s to MACH and pLSI devices.
MAX 3000A devices are available in a wide range of packages, including
PLCC, PQFP, and TQFP packages. See
Table 3
.
Note:
(1)
When the IEEE Std. 1149.1 (JTAG) interface is used for insystem programming or
boundaryscan testing, four I/O pins become JTAG pins.
MAX 3000A devices use CMOS EEPROM cells to implement logic
functions. The userconfigurable MAX 3000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debugging cycles, and can be
programmed and erased up to 100 times.
Table 2. MAX 3000A Speed Grades
Device
Speed Grade
4
5
6
7
10
EPM3032A
v
v
v
EPM3064A
v
v
v
EPM3128A
v
v
v
EPM3256A
v
v
EPM3512A
v
v
Table 3. MAX 3000A Maximum User I/O Pins
Note (1)
Device
44Pin
PLCC
44Pin
TQFP
100Pin
TQFP
144Pin
TQFP
208Pin
PQFP
256-Pin
FineLine
BGA
EPM3032A
34
34
EPM3064A
34
34
66
EPM3128A
80
96
EPM3256A
116
158
EPM3512A
172
208
4
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
MAX 3000A devices contain 32 to 512 macrocells, combined into groups
of 16 macrocells called logic array blocks (LABs). Each macrocell has a
programmable
AND
/fixed
OR
array and a configurable register with
independently programmable clock, clock enable, clear, and preset
functions. To build complex logic functions, each macrocell can be
supplemented with shareable expander and highspeed parallel
expander product terms to provide up to 32 product terms per macrocell.
MAX 3000A devices provide programmable speed/power optimization.
Speedcritical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 3000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when nonspeedcritical signals are switching. The output drivers of all
MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are
2.5V, 3.3V, and 5.0-V tolerant, allowing MAX 3000A devices to be used
in mixedvoltage systems.
MAX 3000A devices are supported by Altera development systems,
which are integrated packages that offer schematic, text--including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)--and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industrystandard PC and UNIXworkstationbased EDA tools. The
software runs on Windowsbased PCs, as well as Sun SPARCstation, and
HP 9000 Series 700/800 workstations.
f
For more information on development tools, see the
MAX+PLUS II
Programmable Logic Development System & Software Data Sheet
and the
Quartus Programmable Logic Development System & Software Data Sheet
.
Functional
Description
The MAX 3000A architecture includes the following elements:
Logic array blocks (LABs)
Macrocells
Expander product terms (shareable and parallel)
Programmable interconnect array (PIA)
I/O control blocks
The MAX 3000A architecture includes four dedicated inputs that can be
used as generalpurpose inputs or as highspeed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin.
Figure 1
shows the architecture of MAX 3000A devices.
Altera Corporation
5
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 1. MAX 3000A Device Block Diagram
Note:
(1)
EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have
10 output enables.
Logic Array Blocks
The MAX 3000A device architecture is based on the linking of
highperformance LABs. LABs consist of 16macrocell arrays, as shown
in
Figure 1
. Multiple LABs are linked together via the PIA, a global bus
that is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
6 or 10
6 or 10
INPUT/GCLRn
6 or 10 Output Enables
(1)
6 or 10 Output Enables
(1)
16
36
36
16
I/O
Control
Block
LAB C
LAB D
I/O
Control
Block
6 or 10
16
36
36
16
I/O
Control
Block
LAB A
Macrocells
1 to 16
LAB B
I/O
Control
Block
6 or 10
PIA
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
2 to 16 I/O
2 to 16 I/O
2 to 16 I/O
2 to 16 I/O
2 to
16
2 to
16
2 to
16
2 to
16
2 to 16
2 to 16
2 to 16
2 to 16
Macrocells
17 to 32
Macrocells
33 to 48
Macrocells
49 to 64
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