Part Number EV3026
October 19, 1999
EV3026
SONET/SDH Clock Recovery Unit
1
EVALUATION BOARD
Description
The S3026 evaluation board provides a flexible plat-
form for verifying the operation of the S3026 Clock
Recovery Unit (CRU). This document provides infor-
mation on the board contents and layout. It should be
used in conjunction with the S3026 data sheet, which
contains full technical details on the chips operation.
The S3026 board is factory configured as "option B"
allowing control of the operating speed via the MODE
signal (SW2) and providing a test point to monitor the
LOCKDET output. Option B allows operation of the
S3026 with either an on-board TTL crystal oscillator or
with an external oscillator connected via the external
TTL REFCLK I/Px connector.
Figure 1. Evaluation Board Layout Top View
AMCC
S3026
SERCLKOP
SERCLKON
SERDATOP
SERDATON
SERDATIP
SERDATIN
AMCC
APPLIED MICRO CIRCUITS CORP.
6290 SEQUENCE DRIVE
SAN DIEGO, CA 92121
S3025/26/27 SONET/SDH CLOCK RECOVERY UNIT
LOCKDETx
GND
I/P
VTT
DUT
VCC
GND
GND
O/P
VTT
BUF
VCC
BUF
VEE
BUFFERED
INPUT
BUFFERED
OUTPUTS
XTAL
TTL XTAL
OSCILLATORx
SW2
LCKREFN
BYPASS
SW3
"0"
"1"
"0"
"1"
EXTERNAL
TTL
REFCLK I/Px
DIPSWITCH OPTIONS
OPT
SQUELCHN
MODE
A
Bx
SW2
SW3
SD
SDN
CRU
OUTPUTS
.
2
EV3026 SONET/SDH Clock Recovery Unit
EVALUATION BOARD
October 19, 1999
Electrical Connections
Power Connections
Terminal posts are provided at the top edge of the
board allowing separate control of voltage levels for
the input signal termination, the S3026 itself, and 1
the S3026 output terminations.
The buffers translate between the external test equip-
ment environment or other standard ECL and/or +5V
referenced ECL systems to supply the correct +5V ref-
erenced ECL to the device. The separately powered
output buffers allow easy connection to the 50
to
ground inputs of high performance oscilloscopes and
spectrum analyzers as well as the standard ECL I/O of
serial Bit Error Rate Testers (BERT) and jitter analyz-
ers. Table 1 illustrates the nominal input voltages for IP
VTT, DUT VCC and O/P VTT. The options for BUF
VEE and BUF VCC are paired vertically.
SMA Connectors
Six coaxial SMA connectors are provided for the differ-
ential serial data input/output signals and output clock.
An additional SMA connector is provided for an
optional external reference clock. (See Figure 1 for
locations.)
Serial Data In [SERDATIP/N] - Buffered Differential
AC coupled PECL inputs. The clock is recovered from
the transitions on these inputs. On-board termination
of 50
to I/P VTT is provided, allowing proper termi-
nation of PECL, ECL, or ground terminated data
sources.
Serial Data Out [SERDATOP/N] - Buffered Differen-
tial PECL outputs. The delayed version of the input
serial data retimed by the recovered serial clock. The
buffered outputs can drive PECL, ECL, or ground ter-
minated instrument inputs. Driven inputs must provide
a 50
DC termination to the respective reference.
These are the recommended outputs for connection of
the evaluation board to monitoring instrumentation.
Serial Clock Out [SERCLKOP/N] - Buffered Differen-
tial PECL outputs. The recovered serial clock, with the
rising edge of SERCLKOP centered in the SERDATOP/
N bit period. The buffered outputs can drive PECL,
ECL, or ground terminated instrument inputs. Driven
inputs must provide a 50
DC termination to the
respective reference. These are the recommended out-
puts for connection of the evaluation board to
monitoring instrumentation.
Note: Accurate measurement also requires the
removal of on-board zero
jumpers for correct imped-
a n c e m a t c h i n g t o e x t e r n a l 5 0
c a b l i n g a n d
instrumentation. Please consult AMCC for appropriate
in-factory reconfiguration.
External TTL Reference Clock [EXTERNAL TTL
REFCLK I/Px] - TTL input providing access to the TLL
Reference Clock (TTLREF) input of the S3026. This
input allows operation at other than the two available
SONET/SDH data rates. The provided TTL crystal
oscillator must be removed if use of an external refer-
ence is desired. This connector can also be used to
monitor the provided TTL oscillator output.
Lock Detect [LOCKDET] - PECL output (Test Point).
In addition to AMS connectors, the LOCKDET output
is available on a test pin post for monitoring with a high
impedance DVM or scope probe.
DIP Switch
The four element DIP switch allows control of the
static inputs of the S3026. The OFF (open = 1) condi-
tion of the DIP switch asserts a logic high on the
assigned signal, and the ON condition asserts a logic
low. In option B, SW2 controls the MODE input. OFF
allows operation at 622.08 Mbit/s, ON selects 155.52
Mbit/s.
SW3 of the DIP switch controls the PECL SDN input.
ON allows the S3026 to recover the clock from the
serial data stream. OFF will force the S3026 to lock to
the reference clock. LCKREFN when ON will also
force the S3026 to lock to the reference clock.
BYPASS should be ON for normal operation.
Table 1. Power Connections for DUT and Test
Equipment Interface
Power Supply
Nominal Input Voltage
I/P VTT
0V / -2.0V / +3V
DUT VCC
5.0V
GND
0.0V
O/P VTT
DUT VCC -2V
BUF VEE
-3.0V / 0.0V / -5.0V
BUF VCC
2.0V / 5.0V / 0.0V
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