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EV3035
SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD
September 22, 1999
EV3035
DESCRIPTION
The S3035 evaluation board provides a flexible platform for verifying the operation of the S3035 transceiver
interface circuit. This document provides information on the board contents. It should be used in conjunction with
the S3035 data sheet, which contains full technical details on the chips operation.
Figure 1 shows the outline of the S3035 evaluation board. Figure 2 shows the block diagram of how the S3035
evaluation board should be connected to test equipment for Bit Error Rate (BER) testing.
SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD
Figure 1. S3035 Evaluation Board Top View
GND
GND
GND
(RSD0P) 1
RSDP
(RSD0N) 1
RSDN
(RSD1P) 1
RSCLKP
(RSD1N) 1
RSCLKN
(TSD1P) 1
TSCLKP
(TSD1N) 1
TSCLKN
(TSD0N) 1
TSDN
(TSD0P) 1
TSDP
DUT
VEE
GND
DUT
VCC
REFCLKP
REFCLKN
TTLREF
GND
1(51MHZCLK) T51MCLK
1(38MHZCLK) T38MCLK
1(19MHZCLK) T19MCLK
1(Not Used) PARERR
POCLK
PCLK
PICLK
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
GND
POUT7:0
PIN7:0
GND
OPEN
FOR NC
RXLOCKDET
1(Not Used) PAROUT
FP
GND
RSTB
"1"
"0"
TSTRST
LLEB
RLPTIME (OE1)
1
SQUELCH (RSDSEL)
1
SDTTL
SDPECL
DLEB
OOF
BYPASS (TESTEN)
1
MODE1
MODE0
SLPTIME
PARIN (OE0)
1
NC
"1"
"0"
6290 SEQUENCE DR.
SAN DIEGO, CA 92121
APPLIED MICRO CIRCUITS CORPORATION
S3035 SONET/SDH/ATM 0C-3/12 TRANSCEIVER WITH CDR
(MODE JUMPERS)
S3035
Note:
1. Signal names in parenthesis are the names for the S3035 transceiver. The signal names not in parenthesis are the signal names on the
actual evaluation board.
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SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD
EV3035
September 22, 1999
Figure 2 depicts how the S3035 evaluation board can be connected for BER measurements, and shows all of
the DIP switch settings. In addition, it shows the Level Shifted ECL (LSECL) power supply requirements for use
with test equipment that utilizes 50
to ground termination. In this configuration the S3035 is configured for use
with the internal S3035 Clock Recovery Unit (CRU), using a 19.44 MHz reference and operating at STS-12.
Figure 2. S3035 Bit Error Rate (BER) Test Setup
S3035 DUT
BERT TX (622MHz)
RSD0P
RSD0N
RSD1P
RSD1N
TSD0P
TSD0N
TSD1P
TSD1N
REFCLKP
REFCLKN
TTLREF
HP8133 PULSE
GENERATOR OR DIVIDER
BERT RX
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
CLOCK
EXT IN
OUT
(DIV BY 32)
OUT
S3035 BER
TEST
19.44MHz
+2V
POWER SUPPLY
DUT VCC = +2V
DUT VEE = -1.3V
5%
GND = 0V
DIP SWITCH SETTINGS:
TSTRST '0'
LLEB '1'
OE1 '0'
RSDSEL '0'
SDTTL '1'
SDPECL '0'
DLEB '1'
OOF '0'
MODE1 '0'
MODE0 '0'
TESTEN '0'
SLPTIME '0'
OE0 '0'
622MHz
LSECL CONFIGURATION
50
+1.2V
+0.2V
+0.7V
10k
FOR Example
19.44 MHz operation
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EV3035
SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD
September 22, 1999
ELECTRICAL CONNECTIONS
Power Connections
Terminal posts are provided at the top edge of the board for VCC and VEE. The S3035 evaluation board can be
configured with ECL, PECL and Level Shifted (LSECL) I/O, so the board can be configured to operate with
different types of standard test equipment. Figures 3 through 5 demonstrate the different types of input and
output waveforms that the S3035 evaluation board can operate with the different voltage settings of VCC and
VEE per Table 1. Note the TTL I/O's voltage level will change to non-standard levels when the S3035 evaluation
board is powered by the different voltage.
The external test equipment environment or other standard ECL and/or +3.3V referenced ECL systems can
interface to the S3035 evaluation board. The board as shown by Figures 1 and 2 can be powered to allow easy
connection to the 50
to ground inputs of high performance oscilloscopes and spectrum analyzers as well as
the standard ECL I/O of serial Bit Error Rate Testers (BERT) and jitter analyzers. Table 1 illustrates the nominal
input voltages for the DUT VCC and VEE voltage levels shown in Figures 3 through 5. Figures 3 and 4 show that
the voltages track with VEE, and Figure 5 shows that the voltages track with VCC.
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Table 1. Power Connections for DUT and Test Equipment Interface
VCC = 0V
-0.8V
-1.3V
-1.8V
Termination = 50
to -2V
VEE = -3.3V +/- 5%
LVECL
Figure 3. LVECL Signal Waveform
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SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD
EV3035
September 22, 1999
SMA Connectors
SMA connectors are provided for the differential serial
data input/output signals. Additional SMA connectors
are provided for an optional differential serial input
clock, the external TTL reference clock and the op-
tional external parallel input clock.
Receive Serial Data [RSD0P/N] -- Differential
LVPECL inputs. Serial data inputs of the S3035. La-
beled as RSDP/N on the evaluation board.
Receive Serial Data [RSD1P/N] -- Differential
LVPECL inputs. Serial data inputs of the S3035. La-
beled as RSCLKP/N on the evaluation board.
Transmit Serial Data [TSD0P/N] -- Differential
LVPECL outputs. The serial output data stream from
the transmitter section of the S3035. These outputs
can drive PECL, ECL, or ground terminated instru-
ment inputs depending on the power supply voltages
applied to the S3035 evaluation board. These SMA
connectors are labeled as TSDP/N on the evaluation
board.
Transmit Serial Data [TSD1P/N] -- Differential
LVPECL outputs. The serial output data stream from
the transmitter section of the S3035. These outputs
can drive PECL, ECL, or ground terminated instru-
ment inputs depending on the power supply voltages
applied to the S3035 evaluation board. These SMA
connectors are labeled as TSCLKP/N on the evalua-
tion board
Reference Clock [REFCLKP/N] -- Differential
LVPECL inputs. These inputs must be provided with
a differential level (depending on the power supply volt-
ages) clock of 19.44 MHz, 38.8 MHz, 51.84 MHz or
77.76 MHz as selected by the MODE[1:0] switches of
the DIP switch. These inputs must be connected to a
logic one state (REFCLKP = "1", & REFCLKN = "0" ) if
TTLREF is used.
TTL Reference Clock [TTLREF] -- LVTTL input.
These inputs must be provided with a TTL (swing
levels dependent on the power supply voltages) clock
of 19.44 MHz, 38.88 MHz, 51.84 MHz or 77.76 MHz
as selected by the MODE[1:0] switches of the DIP
switch. These inputs must be tied high if REFCLKP/N
is used.
Parallel I/O Header Terminals
The parallel input (PIN[7:0]) and output (POUT[7:0])
data to and from the S3035 transceiver are available
at a 4 x 9 pin header array at the right edge of the
evaluation board. Ground pin columns are also pro-
vided to allow connection with 0.1" grid shielded rib-
bon cable to parallel data sources and data analyzers.
User selectable jumpers also allow the parallel output
data (POUT[7:0]) and the output byte clock (POCLK)
to be directly connected to the transmitter parallel
data inputs (PIN[7:0]) and the Parallel Input Clock
(PICLK). Note: The board must be supplied with an
external reference via REFCLKP/N for proper opera-
tion. (See Figure 2.)
Parallel Clock [PCLK] -- LVTTL output. The word
rate output reference from the transmitter PLL. This
output is used to coordinate byte-wide transfers via
the parallel data bus.
Termination = 50
to GND
LSECL
VCC = +2V
+1.2V
+0.7V
+0.2V
VEE = -1.3V +/- 5%
LVPECL
VCC = +3.3V +/- 5%
2.5V
2V
1.5V
VEE = 0V
Termination = 50
to (VCC -2V)
Figure 4. LSECL Signal Waveform
Figure 5. LVPECL Signal Waveform
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EV3035
SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD
September 22, 1999
A separate 5-pin header is also provided for three
additional signals. The three signals are identified be-
low:
19 MHz Clock Output [19MHZCLK] -- LVTTL out-
put. A 19.44 MHz output derived from the S3035
PLL available at the header pin for monitoring. This
is labled as T19MCLK on the evaluation board.
38 MHz Clock Output [38MHZCLK] -- LVTTL out-
put. A 38.88 MHz output derived from the S3035
PLL available at the header pin for monitoring. This
is labled as T38MCLK on the evaluation board.
51 MHz Clock Output [51MHZCLK] -- LVTTL out-
put. A 51.84 MHz output derived from the S3035
PLL available at the header pin for monitoring. This
is labled as T51MCLK on the evaluation board.
A separate 4-pin header is also provided for control
of the No Connect (NC) of the MODE[1:0] DIP switch
setting. This allows the S3035 evaluation board to
run in STS-3 mode with different reference voltages
as outlined in the S3035 data sheet. The No Con-
nect (NC) is obtained by removing the header short-
ing jumper. There are two of these jumpers, one for
each MODE[1:0] signal. For proper operation at
least one of these jumpers must remain connected.
A separate 4-pin header is provided for two addi-
tional signals identified below:
Frame Pulse [FP] -- LVTTL output. Indicates frame
boundaries in the incoming data stream (RSDP/N).
Lock Detect [RXLOCKDET] -- LVTTL output. Indi-
cates that the CRU has locked onto the incoming
data stream. This signal is set High when the CRU is
locked.
DIP SWITCHES
The evaluation board is equipped with two DIP
switches, to control the static control functions of the
on-board device. For both arrays the OFF (open = "0")
condition of the DIP switch asserts a logic low on the
assigned signal, and the ON (closed = "1") condition
asserts a logic high. Figure 2 shows the particular DIP
switch settings that are needed for a particular test
case.
RSTB Pushbutton Switch -- This momentary con-
tact switch controls the master reset of the S3035.
Please refer to the S3035 data sheet for details of
the specific control functions. Normal mode for this
master reset input is High. Depressing the switch
connects this input to a logic zero and resets the
S3035.
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