1
S3017/S3018
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
December 10, 1999 / Revision B
BiCMOS PECL CLOCK GENERATOR
DEVICE SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3017/S3018
FEATURES
Complies with ANSI, Bellcore, and ITU-T
specifications
On-chip high-frequency PLL for clock
generation and clock recovery
Supports 622.08 Mbit/s (OC-12/STM-4)
Reference frequency of 77.76 MHz
Interface to both PECL and TTL logic
8-bit TTL datapath
Compact 52 PQFP TEP package
Diagnostic loopback mode
Lock detect
Low jitter PECL interface
< 2.0 Watt per set typically
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add drop multiplexors
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3017/S3018
GENERAL DESCRIPTION
The S3017/S3018 SONET/SDH/ATM transmitter and
receiver chips are fully integrated serialization/
deserialization SONET OC-12 (622.08 Mbit/s) interface
devices. With architecture developed by PMC-Sierra,
Inc., the chipset performs all necessary serial-to-paral-
lel and parallel-to-serial functions in conformance with
SONET/SDH transmission standards. The devices are
suitable for SONET-based ATM applications. Figure 1
shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3017 transmitter
chip allowing the use of a slower external transmit clock
reference. Clock recovery is performed on the S3018
receiver chip by synchronizing its on-chip VCO directly
to the incoming data stream. The S3018 also performs
SONET/SDH frame detection. The chipset can be used
with a 19.44 or 77.76 MHz reference clock, in support of
existing system clocking schemes.
The low jitter PECL interface guarantees compliance
with the bit-error rate requirements of the Bellcore,
ANSI, and ITU-T standards. The S3017 and S3018 are
packaged in a compact 52 PQFP, offering designers a
small package outline.
Figure 1. System Block Diagram
OTX
ORX
S3018
SONET/
SDH/ATM
Receiver
Network
Interface
Processor
Network
Interface
Processor
S3017
SONET/
SDH/ATM
Transmitter
8
8
2
S3017/S3018
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
December 10, 1999 / Revision B
SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the optical
level. SONET, together with the Synchronous Digital
Hierarchy (SDH) administered by the ITU-T, forms a
single international standard for fiber interconnect be-
tween telephone networks of different countries. SONET
is capable of accommodating a variety of transmission
rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
Photonic
Section
Line
Path
Figure 2 shows the layers and their functions. Each of
the layers has overhead bandwidth dedicated to admin-
istration and maintenance. The photonic layer simply
handles the conversion from electrical to optical and
back with no overhead. It is responsible for transmitting
the electrical signals in optical form over the physical
media. The section layer handles the transport of the
framed electrical signals across the optical cable from
one end to the next. Key functions of this layer are
framing, scrambling, and error monitoring. The line
layer is responsible for the reliable transmission of the
path layer information stream carrying voice, data, and
video signals. Its main functions are synchronization,
multiplexing, and reliable transport. The path layer is
responsible for the actual transport of services at the
appropriate signaling rates.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport
signal level-1 (STS-1). An STS-
N signal is made up of
Elec.
ITU-T
Optical Data Rate (Mbit/s)
STS-1
OC-1
51.84
STS-3
STM-1
OC-3
155.52
STS-12
STM-4
OC-12
622.08
STS-24
OC-24
1244.16
STS-48 STM-16
OC-48 2488.32
N byte-interleaved STS-1 signals. The optical counter-
part of each STS-
N signal is an optical carrier level-N
signal (OC-
N). The S3017/S3018 chipset supports OC-
12 rates (622.08 Mbit/s).
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for STS-12
consists of 36 transport overhead bytes followed by
Synchronous Payload Envelope (SPE) bytes. This pat-
tern of 36 overhead and 1044 SPE bytes is repeated
nine times in each frame. Frame and byte boundaries
are detected using the A1 and A2 bytes found in the
transport overhead. (See Figure 3.)
For more details on SONET operations, refer to the
ANSI SONET standard document.
Figure 3. STS12/OC12 Frame Format
0 bps
Figure 2. SONET Structure
End Equipment
Payload to
SPE mapping
Maintenance,
protection,
switching
Optical
transmission
Scrambling,
framing
Fiber Cable
End Equipment
Section layer
Photonic layer
Line layer
Path layer
Path layer
Section layer
Photonic layer
Line layer
Layer Overhead
(Embedded Ops
Channel)
Functions
576 Kbps
192 Kbps
Table 1. SONET Signal Hierarchy
9 Rows
12 A1
Bytes
12 A2
Bytes
A1 A1
A1 A1
A2 A2
A2 A2
Transport Overhead 36 Columns
36 x 9 = 324 bytes
Synchronous Payload Envelope 1044 Columns
1044 x 9 = 9396
125
sec
v
v
3
S3017/S3018
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
December 10, 1999 / Revision B
S3017/S3018 OVERVIEW
The S3017 transmitter and S3018 receiver implement
SONET/SDH serialization/deserialization, transmission,
and frame detection/recovery functions. The block dia-
grams in Figures 4 and 5 show basic operation of both
chips. These chips can be used to implement the front
end of SONET equipment, which consists primarily of
the serial transmit interface (S3017) and the serial
receive interface (S3018). The chipset handles all the
functions of these two elements, including parallel-to-
serial and serial-to-parallel conversion, clock generation
and recovery, and system timing. The system timing
circuitry consists of management of the datastream,
framing, and clock distribution throughout the front end.
Operation of the S3017/S3018 chips is straightforward.
The sequence of operations is as follows:
Transmitter
1. 8-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
AMCC CONGO (S1201)
POS/ATM SONET Mapper
AMCC NILE
(S1202)
ATM SONET Mapper
AT&T ASTROTEC1227/1230
650 Mbit/s
Fiber Optic Transmitter
Mitsubishi MF-622DF-T12-XXX
622 Mbit/s
Fiber Optic Transmitter
Sumitomo ES-9304-TD
622 Mbit/s
Fiber Optic Transmitter
AT&T ASTROTEC 1310
650 Mbit/s
Fiber Optic Receiver
Mitsubishi MF-622DS-R1X-XXX
622 Mbit/s
Fiber Optic Receiver
Sumitomo ES-9216-RD
622 Mbit/s
Fiber Optic Receiver
Finisar
1000 Mbit/s
Fiber Optic Transceiver
Suggested Interface Devices
Receiver
1. Clock and data recovery from serial input
2. Frame detection
3. Serial-to-parallel conversion
4. 8-bit parallel output
Internal clocking and control functions are transparent
to the user. Details of data timing can be seen in Figures
9 through 14.
A lock detect feature is provided on the S3018, which
indicates that the PLL is locked (synchronized) to the
data stream, and facilitates continuous down-stream
clocking in the absence of data.
Figure 4. S3017 Transmitter Functional Block Diagram
8
2
PIN[7:0]
8:1 PARALLEL
TO SERIAL
LPDATOP/N
SERDATOP/N
PICLK
TIMING
GEN
PCLK
REFCKINP/N
CLOCK
SYNTHESIZER
RSTB
D
2
TSTCLKEN
REFSEL
LOCLPEN
TSCLKSEL
2
TESTRST
CAP1
CAP2
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S3017/S3018
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
December 10, 1999 / Revision B
S3017 TRANSMITTER
FUNCTIONAL DESIGN
The S3017 transmitter chip performs the serializing stage
in the processing of a transmit SONET STS-12 bit serial
data stream. It converts the byte serial 77.76 Mbyte/sec
data stream to bit serial format at 622.08 Mbit/sec.
A high-frequency bit clock can be generated from a
77.76 MHz frequency reference by using an integral
frequency synthesizer consisting of a phase-locked
loop circuit with a divider in the loop.
Diagnostic loopback is provided (transmitter to receiver)
when used with the compatible S3018. (See Other
Operating Modes.)
Clock Synthesizer
The Clock Synthesizer, shown in the block diagram in
Figure 4, is a monolithic PLL that generates the serial
output clock phase synchronized with the input refer-
ence clock (REFCKINP/N).
The REFCKINP/N input must be generated from a
differential PECL crystal oscillator which has a fre-
quency accuracy of better than 20 ppm in order for the
TSCLK frequency to have the same accuracy required
for operation in a SONET system. Lower accuracy
crystal oscillators may be used in applications less
demanding than SONET/SDH.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO out-
put and the REFCKINP/N input, a loop filter which converts
the phase detector output into a smooth DC voltage,
and a VCO, whose frequency is varied by this voltage.
The loop filter generates a VCO control voltage based
on the average DC level of the phase discriminator
output pulses. A single external clean-up capacitor is
utilized as part of the loop filter. The loop filter's corner
frequency is optimized to minimize output phase jitter.
Figure 5. S3018 Receiver
1:8 SERIAL
TO PARALLEL
TIMING
GEN
M
U
X
REFCKINP/N
REFSEL
CLOCK
RECOVERY
TSTCLKEN
SERDATIP/N
LPDATIP/N
FRAME
BYTE
DETECT
LOCLPEN
OOF
FP
POUT[7:0]
8
2
LOS
RSTB
BACKUP
REFERENCE
GEN
POCLK
LOCKDET
CAP1
CAP2
2
2
5
S3017/S3018
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
December 10, 1999 / Revision B
25k 65k
250k
6.5k
300
30
0.15
1.5
15
Jitter Frequency (Hz)
Jitter
Amplitude
(Ul p-p)
Minimum proposed
tolerance
(TA-NWT-000253)
Figure 6. Clock Recovery Jitter Tolerance
OC-12
Figure 6. Clock Recovery Jitter Tolerance
Timing Generator
The Timing Generation function, seen in Figure 4,
provides a byte rate version of the transmit serial clock.
This circuitry also provides an internally generated load
signal, which transfers the PIN[7:0] data from the paral-
lel input register to the serial shift register.
The PCLK output is a byte rate version of transmit serial
clock at 77.76 MHz. PCLK is intended for use as a byte
speed clock for upstream multiplexing and overhead
processing circuits. Using PCLK for upstream circuits will
ensure a stable frequency and phase relationship between
the data coming into and leaving the S3017 device.
Parallel-to-Serial Converter
The Parallel-to-Serial converter shown in Figure 4 is
comprised of two byte-wide registers. The first register
latches the data from the PIN[7:0] bus on the rising edge
of PICLK. The second register is a parallel loadable shift
register which takes its parallel input from the first
register.
The load signal, which latches the data from the parallel
to the serial shift register, has a fixed relationship to
PCLK. If PICLK is tied to PCLK, the PIN[7:0] data
latched into the parallel register will meet the timing
specifications with respect to the load signal. If PICLK
is not tied to PCLK, the delay must meet the timing
requirements shown in Figure 9, and PICLK must be
frequency locked to the reference clock input.
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