1
S3033
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
April 7, 2000 / Revision D
BiCMOS LVPECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3033
FEATURES
Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLL for clock
generation
Supports 155.52 Mbps (OC-3) and 622.08
Mbps (OC-12)
Selectable reference frequencies of 19.44,
38.88, 51.84 or 77.76 MHz
Interface to both LVPECL and TTL logic
8-bit TTL data path
Compact 10 mm 64 PQFP/TEP package
Diagnostic loopback mode
Low jitter LVPECL interface
Single 3.3V supply
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
Figure 1. System Block Diagram
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
S3033
GENERAL DESCRIPTION
The S3033 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET OC-12
(622.08 Mbps) and OC-3 (155.52 Mbps) interface de-
vice. The chip performs all necessary serial-to-parallel
and parallel-to-serial functions in conformance with
SONET/SDH transmission standards. The device is
suitable for SONET-based ATM applications. Figure 1
shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3033
transceiver chip allowing the use of a slower external
transmit clock reference. The S3033 performs
SONET/SDH frame detection. The chip can be used
with 19.44, 38.88, 51.84 or 77.76 MHz reference
clocks, in support of existing system clocking
schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3033 is pack-
aged in a 10 mm 64 PQFP/TEP, offering designers a
small package outline.
S3033
SONET/SDH
Transceiver
Network
Interface
Processor
Network
Interface
Processor
S3033
SONET/SDH
Transceiver
OTX
ORX
OTX
ORX
8
8
8
8
S3024
S3024
2
S3033
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
April 7, 2000 / Revision D
SONET OVERVIEW
Synchronous Optical Network (SONET) is a stan-
dard for connecting one fiber system to another at
the optical level. SONET, together with the Synchro-
nous Digital Hierarchy (SDH) administered by the
ITU-T, forms a single international standard for fiber
interconnect between telephone networks of differ-
ent countries. SONET is capable of accommodating
a variety of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
Photonic
Section
Line
Path
Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to opti-
cal and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream
carrying voice, data, and video signals. Its main
functions are synchronization, multiplexing, and reli-
able transport. The path layer is responsible for the
actual transport of services at the appropriate signal-
ing rates.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport
signal level-1 (STS-1). An STS-
N signal is made up
of
N byte-interleaved STS-1 signals. The optical
counterpart of each STS-
N signal is an optical carrier
level-
N signal (OC-N). The S3033 chip supports OC-3
and OC-12 rates (155.52 and 622.08 Mbps).
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for
STS-12 consists of 36 transport overhead bytes fol-
lowed by Synchronous Payload Envelope (SPE)
bytes. This pattern of 36 overhead and 1044 SPE bytes
is repeated nine times in each frame. Frame and byte
boundaries are detected using the A1 and A2 bytes
found in the transport overhead. (See Figure 3.)
For more details on SONET operations, refer to the
Bellcore SONET standard document.
Elec.
CCITT
Optical Data Rate (Mbps)
STS-1
OC-1
51.84
STS-3
STM-1
OC-3
155.52
STS-12
STM-4
OC-12
622.08
STS-24
STM-8
OC-24
1244.16
STS-48 STM-16
OC-48 2488.32
Table 1. SONET Signal Hierarchy
Figure 2. SONET Structure
Figure 3. STS12/OC12 Frame Format
9 Rows
12 A1
Bytes
12 A2
Bytes
A1 A1
A1 A1
A2 A2
A2 A2
Transport Overhead 36 Columns
36 x 9 = 324 bytes
Synchronous Payload Envelope 1044 Columns
1044 x 9 = 9396 bytes
125
sec
v
v
0 bps
End Equipment
Payload to
SPE mapping
Maintenance,
protection,
switching
Optical
transmission
Scrambling,
framing
Fiber Cable
End Equipment
Section layer
Photonic layer
Line layer
Path layer
Path layer
Section layer
Photonic layer
Line layer
Layer Overhead
(Embedded Ops
Channel)
Functions
576 Kbps
192 Kbps
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S3033
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
April 7, 2000 / Revision D
S3033 OVERVIEW
The S3033 transceiver implements SONET/SDH se-
rialization/deserialization, transmission, and frame
detection/recovery functions. The block diagram in
Figure 4 shows the basic operation of the chip. This
chip can be used to implement the front end of
SONET equipment, which consists primarily of the
serial transmit interface and the serial receive inter-
face. The chip handles all the functions of these two
elements, including parallel-to-serial and serial-to-par-
allel conversion, clock generation, and system
timing. The system timing circuitry consists of man-
agement of the data stream, framing, and clock
distribution throughout the front end.
The S3033 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:
Transmitter Operations:
1. 8-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver Operations:
1. Frame detection
2. Serial-to-parallel conversion
3. 8-bit parallel output
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 7 through 10.
Figure 4. S3033 Transceiver Functional Block Diagram
1:8 SERIAL
TO PARALLEL
TIMING
GEN
M
U
X
DECISION
CKT
RSDP/N
FRAME
BYTE
DETECT
DLEB
OOF
FP
POUT[7:0]
8
SDTTL
POCLK
8
PIN[7:0]
8:1 PARALLEL
TO SERIAL
TSDP/N
PICLK
TIMING
GEN
PCLK
19MHZCLK
CLOCK
SYNTHESIZER
RSTB
D
TSTRST
MODE0
MODE1
CAP1
CAP2
Transmitter
Receiver
TSCLKP/N
LLEB
SLPTIME
REFCLKP/N
TTLREF
SDPECL
RLPTIME
TSCLKP/N
RSCLKP/N
Suggested Interface Devices
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S3033
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
April 7, 2000 / Revision D
S3033 TRANSCEIVER
FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
The S3033 transceiver chip performs the serializing
stage in the processing of a transmit SONET STS-3
or STS-12 bit serial data stream. It converts the 8-bit
parallel 19.44 or 77.76 Mbyte/sec data stream into
bit serial format at 155.52 or 622.08 Mbps.
A high-frequency bit clock can be generated from a
19.44 or 77.76 MHz frequency reference by using an
integral frequency synthesizer consisting of a phase-
locked loop circuit with a divider in the loop.
Diagnostic loopback is provided (transmitter to re-
ceiver). See Other Operating Modes.
Clock Synthesizer
The clock synthesizer, shown in the block diagram in
Figure 4, is a monolithic PLL that generates the se-
rial output clock phase synchronized with the input
reference clock (REFCLKP/N or TTLREF).
The REFCLKP/N or TTLREF input must be gener-
ated from a crystal oscillator which has a frequency
accuracy that meets the value stated in Table 8 in
order for the TSCLK frequency to have the same
accuracy required for operation in a SONET system.
Lower accuracy crystal oscillators may be used in
applications less demanding than SONET/SDH.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLKP/N or TTLREF input, a loop
filter which converts the phase detector output into a
smooth DC voltage, and a VCO, whose frequency is
varied by this voltage.
The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter's corner frequency is optimized to minimize out-
put phase jitter.
Timing Generator
The timing generation function, seen in Figure 4,
provides an 8-bit parallel rate version of the transmit
serial clock. This circuitry also provides an internally gen-
erated load signal, which transfers the PIN[7:0] data
from the parallel input register to the serial shift reg-
ister.
The PCLK output is an 8-bit parallel rate version of
the transmit serial clock at 19.44 or 77.76 MHz.
PCLK is intended for use as an 8-bit parallel speed
clock for upstream multiplexing and overhead pro-
cessing circuits. Using PCLK for upstream circuits
will ensure a stable frequency and phase relation-
ship between the data coming into and leaving the
S3033 device.
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is
comprised of two 8-bit registers. The first register
latches the data from the PIN[7:0] bus on the rising
edge of PICLK. The second register is a parallel
loadable shift register which takes its parallel input
from the first register.
The load signal, which latches the data from the par-
allel to the serial shift register, has a fixed
relationship to PCLK. If PICLK is tied to PCLK, the
PIN[7:0] data latched into the parallel register will
meet the timing specifications with respect to the
load signal. If PICLK is not tied to PCLK, the delay
must meet the timing requirements shown in Figure 8.
Table 2. Reference Frequency Options
Table 3. Reference Jitter Limits
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5
S3033
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
April 7, 2000 / Revision D
RECEIVER OPERATION
The S3033 transceiver chip provides the first stage
of the digital processing of a receive SONET STS-3
or STS-12 bit-serial stream. It converts the bit-serial
155.52 or 622.08 Mbps data stream into a 19.44 or
77.76 Mbyte/sec 8-bit parallel data format.
A loopback mode is provided for diagnostic loopback
(transmitter to receiver).
Frame and Byte Boundary Detection
The frame and byte boundary detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by three consecutive A2
bytes. Framing pattern detection is enabled and dis-
abled by the Out-Of-Frame (OOF) input. Detection is
enabled by a rising edge on OOF, and remains en-
abled for the duration that OOF is active. It is
disabled when a framing pattern is detected and
OOF is inactive. When framing pattern detection is
enabled, the framing pattern is used to locate byte
and frame boundaries in the incoming data stream
(RSD or looped transmitter data). The timing genera-
tor block takes the located byte boundary and uses it
to block the incoming data stream into bytes for out-
put on the parallel output data bus (POUT[7:0]). The
frame boundary is reported on the Frame Pulse (FP)
output when any 48-bit pattern matching the framing
pattern is detected on the incoming data stream.
When framing pattern detection is disabled, the byte
boundary is frozen to the location found when detec-
tion was previously enabled. Only framing patterns
aligned to the fixed byte boundary are indicated on
the FP output.
The probability that random data in an STS-3 or STS-
12 stream will generate the 48-bit framing pattern is
extremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. There-
fore, the time to match the first frame pattern and to
verify it with down-stream circuitry, at the next occurrence
of the pattern, is expected to be less than the required
250
s, even for extremely high bit error rates.
Once down-stream overhead circuitry has verified
that the frame and byte synchronization are correct,
the OOF input can be set low to disable the frame
search process from trying to synchronize to a mimic
frame pattern
Serial-to-Parallel Converter
The serial-to-parallel converter consists of three 8-bit
registers. The first is a serial-in, parallel-out shift reg-
ister, which performs serial-to-parallel conversion
clocked by the clock recovery block. The second is
an 8-bit internal holding register, which transfers
data from the serial to parallel register on byte
boundaries as determined by the frame and byte
boundary detection block. On the falling edge of the
free running POCLK, the data in the holding register
is transferred to an output holding register which
drives POUT[7:0].
The delay through the serial-to-parallel converter
can vary from 1.5 to 2.5 byte periods (12 to 20 serial
bit periods) measured from the first bit of an incom-
ing byte to the beginning of the parallel output of that
byte. The variation in the delay is dependent on the
alignment of the internal parallel load timing, which is
synchronized to the data byte boundaries, with respect
to the falling edge of POCLK, which is independent of
the byte boundaries. The advantage of this serial to
parallel converter is that POCLK is neither truncated
nor extended during reframe sequences.
(See Figure 11.)
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