1
S3035
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
April 12, 2000 / Revision D
BiCMOS LVPECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
S3035
FEATURES
Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLLs for clock
generation and clock recovery
Supports 155.52 Mbit/s (OC-3) and 622.08
Mbit/s (OC-12)
Selectable reference frequencies of 19.44,
38.88, 51.84 or 77.76 MHz
Interface to both LVPECL and TTL logic
Redundant receiver inputs
Redundant transmitter outputs
8-bit TTL data path
Compact 14 mm 80 PQFP package
Diagnostic loopback mode
Lock detect
Low jitter LVPECL interface
Single 3.3 V supply
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminator
Fiber optic test equipment
ATM switch backbones requiring redundancy
Figure 1. System Block Diagram
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
S3035
GENERAL DESCRIPTION
The S3035 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET
OC-12 (622.08 Mbit/s) and OC-3 (155.52 Mbit/s) in-
terface device. The chip performs all necessary
serial-to-parallel and parallel-to-serial functions in
conformance with SONET/SDH transmission stan-
dards. The device is suitable for SONET-based ATM
applications. Figure 1 shows a typical network appli-
cation.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3035
transceiver chip allowing the use of a slower external
transmit clock reference. Clock recovery is performed
on the device by synchronizing its on-chip VCO directly
to the incoming data stream. The S3035 also per-
forms SONET/SDH frame detection. The chip can be
used with a 19.44, 38.88, 51.84 or 77.76 MHz refer-
ence clock, in support of existing system clocking
schemes. Redundant transmit and receive serial I/O
can be used to implement redundant physical layers
in ATM backbones.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3035 is pack-
aged in a 14 mm 80 PQFP, offering designers a
small package outline.
S3035
SONET/SDH
Transceiver
Network
Interface
Processor
Network
Interface
Processor
S3035
SONET/SDH
Transceiver
OTX
ORX
OTX
ORX
8
8
8
8
OTX
ORX
ORX
OTX
2
S3035
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
April 12, 2000 / Revision D
SONET OVERVIEW
Synchronous Optical Network (SONET) is a stan-
dard for connecting one fiber system to another at
the optical level. SONET, together with the Synchro-
nous Digital Hierarchy (SDH) administered by the
ITU-T, forms a single international standard for fiber
interconnect between telephone networks of differ-
ent countries. SONET is capable of accommodating
a variety of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
Photonic
Section
Line
Path
Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to opti-
cal and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error moni-
toring. The line layer is responsible for the reliable
transmission of the path layer information stream
carrying voice, data, and video signals. Its main
functions are synchronization, multiplexing, and reli-
able transport. The path layer is responsible for the
actual transport of services at the appropriate signal-
ing rates.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designa-
tions of the SONET hierarchy. The lowest level is the
basic SONET signal referred to as the synchronous
transport signal level-1 (STS-1). An STS-
N signal is
made up of
N byte-interleaved STS-1 signals. The
optical counterpart of each STS-
N signal is an opti-
cal carrier level-
N signal (OC-N). The S3035 chip
supports OC-3 and OC-12 rates (155.52 and 622.08
Mbit/s).
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for
STS-12 consists of 36 transport overhead bytes fol-
lowed by Synchronous Payload Envelope (SPE)
bytes. This pattern of 36 overhead and 1044 SPE bytes
is repeated nine times in each frame. Frame and byte
boundaries are detected using the A1 and A2 bytes
found in the transport overhead. (See Figure 3.)
For more details on SONET operations, refer to the
Bellcore SONET standard document.
Elec.
ITU-T
Optical Data Rate (Mbit/s)
STS-1
OC-1
51.84
STS-3
STM-1
OC-3
155.52
STS-12
STM-4
OC-12
622.08
STS-24
STM-8
OC-24
1244.16
STS-48 STM-16
OC-48 2488.32
Table 1. SONET Signal Hierarchy
Figure 2. SONET Structure
0 bps
End Equipment
Payload to
SPE mapping
Maintenance,
protection,
switching
Optical
transmission
Scrambling,
framing
Fiber Cable
End Equipment
Section layer
Photonic layer
Line layer
Path layer
Path layer
Section layer
Photonic layer
Line layer
Layer Overhead
(Embedded Ops
Channel)
Functions
576 Kbps
192 Kbps
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S3035
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
April 12, 2000 / Revision D
Figure 3. STS12/OC12 Frame Format
9 Rows
12 A1
Bytes
12 A2
Bytes
A1 A1
A1 A1
A2 A2
A2 A2
Transport Overhead 36 Columns
36 x 9 = 324 bytes
Synchronous Payload Envelope 1044 Columns
1044 x 9 = 9396 bytes
125
sec
v
v
S3035 OVERVIEW
The S3035 transceiver implements SONET/SDH se-
rialization/deserialization, transmission, and frame
detection/recovery functions. The block diagram in
Figure 4 shows the basic operation of the chip. This
chip can be used to implement the front end of
SONET equipment, which consists primarily of the
serial transmit interface and the serial receive inter-
face. The chip handles all the functions of these two
elements, including parallel-to-serial and serial-to-par-
allel conversion, clock generation and recovery, and
system timing. The system timing circuitry consists
of management of the data stream, framing, and
clock distribution throughout the front end.
The S3035 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:
AMCC CONGO (S1201) POS/ATM SONET Mapper
AMCC NILE (S1202) ATM SONET Mapper
Suggested Interface Devices
Transmitter Operations:
1. 8-bit parallel input
2. Parallel-to-serial conversion
3. Redundant serial output
Receiver Operations:
1. Redundant serial input select
2. Clock and data recovery from serial input
3. Frame detection
4. Serial-to-parallel conversion
5. 8-bit parallel output
Internal clocking and control functions are transpar-
ent to the user.
A lock detect feature is provided on the S3035,
which indicates that the PLL is locked (synchronized)
to the incoming data stream, and facilitates continu-
ous down-stream clocking in the absence of data.
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S3035
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
April 12, 2000 / Revision D
1:8 SERIAL
TO PARALLEL
TIMING
GEN
M
U
X
CLOCK
RECOVERY
TESTEN
FRAME
BYTE
DETECT
DLEB
RSD0P/N
RSD1P/N
RSDSEL
OOF
FP
POUT[7:0]
8
SDTTL
BACKUP
REFERENCE
GEN
POCLK
RXLOCKDET
8
PIN[7:0]
8:1 PARALLEL
TO SERIAL
TSD1P/N
OE1
PICLK
TIMING
GEN
PCLK
38MHZCLK
51MHZCLK
CLOCK
SYNTHESIZER
RSTB
TSTRST
MODE 0
MODE 1
CAP1
CAP2
Transmitter
Receiver
LLEB
SLPTIME
REFCLKP/N
TTLREF
SDPECL
TSD0P/N
OE0
M
U
X
19MHZCLK
D
D
Figure 4. S3035 Transceiver Functional Block Diagram
5
S3035
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
April 12, 2000 / Revision D
S3035 TRANSCEIVER
FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
The S3035 transceiver chip performs the serializing
stage in the processing of a transmit SONET STS-3
or STS-12 bit serial data stream. It converts the 8-bit
parallel 19.44 or 77.76 Mbps data stream into bit
serial format at 155.52 or 622.08 Mbit/sec.
A high-frequency bit clock can be generated from a
19.44 or 77.76 MHz frequency reference by using an
integral frequency synthesizer consisting of a phase-
locked loop circuit with a divider in the loop.
Diagnostic loopback is provided (transmitter to re-
ceiver). See Other Operating Modes.
Clock Synthesizer
The clock synthesizer, shown in the block diagram in
Figure 4, is a monolithic PLL that generates the se-
rial output clock phase synchronized with the input
reference clock (REFCLKP/N or TTLREF).
The REFCLKP/N or TTLREF input must be gener-
ated from a crystal oscillator which has a frequency
accuracy that meets the value stated in Table 7 in
order for the TSD frequency to have the same accu-
racy required for operation in a SONET system.
Lower accuracy crystal oscillators may be used in
applications less demanding than SONET/SDH.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLKP/N or TTLREF input, a loop
filter which converts the phase detector output into a
smooth DC voltage, and a VCO, whose frequency is
varied by this voltage.
The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter's corner frequency is optimized to minimize out-
put phase jitter.
Timing Generation
The timing generation function, seen in Figure 4,
provides a byte rate version of the transmit serial
clock. This circuitry also provides an internally generated
load signal, which transfers the PIN[7:0] data from
the parallel input register to the serial shift register.
The PCLK output is a byte rate version of transmit
serial clock at 19.44 or 77.76 MHz. PCLK is intended
for use as a byte speed clock for upstream multiplex-
ing and overhead processing circuits. Using PCLK
for upstream circuits will ensure a stable frequency
and phase relationship between the data coming into
and leaving the S3035 device.
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is
comprised of two byte-wide registers. The first regis-
ter latches the data from the PIN[7:0] bus on the
rising edge of PICLK. The second register is a paral-
lel loadable shift register which takes its parallel
input from the first register.
The load signal, which latches the data from the par-
allel to the serial shift register, has a fixed
relationship to PCLK. If PICLK is tied to PCLK, the
PIN[7:0] data latched into the parallel register will
meet the timing specifications with respect to the
load signal. If PICLK is not tied to PCLK, the delay
must meet the timing requirements shown in Figure 8.
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Table 2. Reference Frequency Options
Table 3. Reference Jitter Limits
1. Only valid in SLP mode.
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