1
S3051
2.5 GBPS LIMITING AMPLIFIER
July 14, 1999 / Revision B
S3051
2.5 GBPS LIMITING AMPLIFIER
DEVICE
SPECIFICATION
FEATURES
2 GHz Bandwidth
32dB Gain
Single +5V Power Supply
Fully Differential Architecture
16 pin Glass-Metal Package
APPLICATIONS
SONET OC-48
Fiber Optic Data Links
High-Speed FM Limiting Amplifier
Figure 1. System Block Diagram
DIN-
DIN+
DOUT+
DOUT
INPUT
OUT
OUT+
S3051
V
+REF
V
REF
VCC
C
BYP
C
IN
C
IN
C
BYP
GENERAL DESCRIPTION
The S3051 limiting amplifier with its high gain and wide
bandwidth is ideal for use as a post amplifier in fiber
optic receivers with data rates up to 2.5 Gbps. The
amplifier's gain is 32dB, and differential signals as
small as 12 mVp-p, can be amplified to 900 mVp-p.
Figure 1 shows a typical system application.
2
S3051
2.5 GBPS LIMITING AMPLIFIER
July 14, 1999 / Revision B
DETAILED DESCRIPTION
The S3051 is an integrated limiting amplifier in-
tended for high-frequency fiber-optic applications.
The circuit connects to typical transimpedance am-
plifiers found within a fiber-optic link. The linear
signal output from a transimpedance amplifier can
contain significant amounts of noise, and may vary
in amplitude over time. The S3051 limiting amplifier
quantizes the signal, and outputs a voltage limited
waveform over a 38 dB input dynamic range.
At low signal levels, below 12 mVp-p, the circuit be-
haves as a linear amplifier. At higher levels the
device becomes a limiting amplifier.
Figure 2. Functional Block Diagram
DOUT
DOUT+
DIN
DIN+
V
REF
V+
REF
50
11
10
9
8
7
6
5
4
3
12
2
1
16
15
14
13
NC
VCC(OB)
VCC(GS1,SS2)
GND(OB)
GND(OB)
GND(OB)
GND(OB)
GND(GS1,GS2)
GND(GS1,GS2)
5k
5k
VCC(GS1,GS2)
VCC= +5V
GS1
GS2
OB
110pF
110pF
NC ..... No Connect
50
5k
5k
The referred wideband input noise (160
Vrms) al-
lows for a less than 1E-9 Bit Error Rate for inputs
down to 2 mVp-p.
The S3051 is designed to allow adjustment of the
DC offset between the DIN+ and DIN inputs. V
+REF
can be used as a reference from which the required
offset can be subtracted to set the DC bias level at
DIN. Similarly, V
REF
can be used to set the DC
bias level at DIN+. (See Application Information).
If no adjustment is made to the input DC bias level,
two resistors can be connected in a negative feed-
back configuration in order to cancel any DC offset
at the input. This will minimize the pulse width distor-
tion. (See separate S3051 Limiting Amplifier
Application document.)
3
S3051
2.5 GBPS LIMITING AMPLIFIER
July 14, 1999 / Revision B
Table 1. S3051 Pin Assignment and Descriptions
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4
S3051
2.5 GBPS LIMITING AMPLIFIER
July 14, 1999 / Revision B
Figure 3. S3051 16-Pin Glass-Metal Package
e
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w
o
P
x
a
M
a
j
1
5
0
3
S
W
m
0
5
7
W
/
C
0
6
Thermal Management
5
S3051
2.5 GBPS LIMITING AMPLIFIER
July 14, 1999 / Revision B
Figure 4. S3051 Pinout (Top View)
S3051
TOP VIEW
16 Lead Flat Pack
1
2
3
4
12
11
10
9
16
15
14
13
5
6
7
8
GND
DOUT+
DOUT
GND
GND
GND
VCC
NC
DIN+
V+REF
DIN-
VREF
GND
GND
VCC
VCC
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