S3059

MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER

October 31, 2000 / Revision B

BiCMOS LVPECL CLOCK GENERATOR

DEVICE
SPECIFICATION

SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER

S3059

FEATURES

· SiGe BiCMOS technology
· Complies with Bellcore and ITU-T

specifications

· On-chip high-frequency PLL for clock

generation

· Supports OC-48 (2488.32 Mbps)

OC-24 (1244.16 Mbps)
Gigabit Ethernet (1250 Mbps)
OC-12 (622.08 Mbps)
OC-3 (155.52 Mbps)

· Reference frequency of 155.52 MHz
· Interface to LVPECL and LVTTL logic
· 16-bit differential LVPECL datapath
· Compact 218 TBGA package
· Diagnostic loopback mode
· Supports line timing
· Lock detect
· Signal detect input
· Low jitter LVPECL interface
· Internal FIFO to decouple transmit clocks
· Single 3.3 V supply
· Typical power 1.7 W

APPLICATIONS

· Wavelength Division Multiplexing (WDM)

equipment

· SONET/SDH-based transmission systems
· SONET/SDH modules
· SONET/SDH test equipment
· ATM over SONET/SDH
· Section repeaters
· Add Drop Multiplexers (ADM)
· Broad-band cross-connects
· Fiber optic terminators
· Fiber optic test equipment

Figure 1. System Block Diagram

MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER

S3059

GENERAL DESCRIPTION

The S3059 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET
OC-48 (2488.32 Mbps), OC-24 (1244.16 Mbps), Gi-
gabit Ethernet (1250 Mbps), OC-12 (622.08 Mbps)
and OC-3 (155.52 Mbps) interface device. The chip
performs all necessary serial-to-parallel and parallel-
to-serial functions in conformance with SONET/SDH
transmission standards. The device is suitable for
SONET-based WDM applications. Figure 1 shows a
typical network application.

On-chip clock synthesis is performed by the high-
frequency Phase Locked Loop (PLL) on the S3059
transceiver chip allowing the use of a slower external
transmit clock reference. The chip can be used with
a 155.52 MHz reference clock in support of existing
system clocking schemes.

The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3059 is pack-
aged in a 218 TBGA, offering designers a small
package outline.

Network Interface

Processor

Network Interface

Processor

S3059

OTX

ORX

OTX

ORX

S3056

S3059

MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER

October 31, 2000 / Revision B

S3059 OVERVIEW

The S3059 transceiver implements SONET/SDH
serialization/deserialization, and transmission func-
tions. The block diagram in Figure 2 shows the basic
operation of the chip. This chip can be used to
implement the front end of SONET equipment, which
consists primarily of the serial transmit interface and
the serial receive interface. The chip handles all the
functions of these two elements, including parallel-to-
serial and serial-to-parallel conversion, clock
generation, and system timing. The system timing
circuitry consists of management of the data stream
and clock distribution throughout the front end. The
suggested interface devices are given in Table 2.

The S3059 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:

Transmitter Operations:

1. 16-bit parallel input
2. Parallel-to-serial conversion
3. Serial output

Receiver Operations:

1. Serial input
2. Serial-to-parallel conversion
3. 16-bit parallel output

Internal clocking and control functions are transpar-
ent to the user.

Table 1. Data Rate Select

Table 2. Suggested Interface Devices

S3059

MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER

October 31, 2000 / Revision B

S3059 TRANSCEIVER
FUNCTIONAL DESCRIPTION

TRANSMITTER OPERATION

The S3059 transceiver chip performs the serializa-
tion stage in the processing of a transmit SONET
STS-48/STS-24/STS-12/STS-3/GBE data stream
depending on the data rate selected. It converts
16-bit parallel data into bit-serial format at 2488.32/
1244.16/622.08/155.52/1250 Mbps.

A high-frequency bit clock can be generated from a
155.52 MHz frequency reference by using an inte-
gral frequency synthesizer consisting of a
phase-locked loop circuit with a divider in the loop.

Diagnostic loopback (transmitter to receiver) and line
loopback (receiver to transmitter) is provided. See
Other Operating Modes.

Clock Synthesizer

The clock synthesizer, shown in the block diagram in
Figure 2, is a monolithic PLL that generates the se-
rial output clock frequency locked to the input
Reference Clock (REFCLKP/N).

The REFCLKP/N input must be generated from a
crystal oscillator which has a frequency accuracy of
better than the value stated in Table 8 in order for
the Transmit Serial Clock (TSCLK) frequency to
have the same accuracy required for operation in a
SONET system. Lower accuracy crystal oscillators
may be used in applications less demanding than
SONET/SDH.

The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLKP/N input, a loop filter which
converts the phase detector output into a smooth DC
voltage, and a VCO, whose frequency is varied by
this voltage.

The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter's corner frequency is optimized to minimize out-
put phase jitter.

Timing Generation

The timing generation function, seen in Figure 2, pro-
vides a divide by 16 rate version of the transmit
serial clock. This circuitry also provides an internally
generated load signal, which transfers the PINP/
N[15:0] data from the FIFO to the serial shift register.

The PCLK output is a divide by 16 rate version of
transmit serial clock (divide by 16). PCLK is intended
for use as a divide by 16 clock for upstream multi-
plexing and overhead processing circuits. Using
PCLK for upstream circuits will ensure a stable fre-
quency and phase relationship between the data
coming into and leaving the S3059 device.

The timing generator also produces a feedback ref-
erence clock to the clock synthesizer. A counter
divides the synthesized clock down to the same fre-
quency as the REFCLK. The PLL in the clock
synthesizer maintains the stability of the synthesized
clock by comparing the phase of the internal clock
with that of the REFCLK.

Table 3. Reference Jitter Limits

S3059

MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER

October 31, 2000 / Revision B

Parallel-to-Serial Converter

The parallel-to-serial converter shown in Figure 2 is
comprised of a FIFO and a parallel-to-serial register.
The FIFO input latches the data from the PINP/N[15:0]
bus on the rising edge of PICLK. The parallel-to-serial
register is a loadable shift register which takes its paral-
lel input from the FIFO output.

An internally generated divide by 16 clock, which is
phase aligned to the transmit serial clock as de-
scribed in the timing generator description, activates
the parallel data transfer between registers. The serial
data is shifted out of the parallel-to-serial register at
the TSCLK rate.

FIFO

A FIFO is added to decouple the internal and exter-
nal (PICLK) clocks. The internally generated divide
by 16 clock is used to clock out data from the FIFO.
Phase Initialization (PHINIT) and Lock Detect
(LOCKDET) are used to center or reset the FIFO.
The PHINIT and LOCKDET signals will center the
FIFO after the third PICLK pulse. This is in order to
insure that PICLK is stable. This scheme allows the
user to have an infinite PCLK to PICLK delay
through the ASIC. Once the FIFO is centered, the
PCLK to PICLK delay can have a maximum drift
specified by Table 18.

FIFO Initialization

The FIFO can be initialized in one of the following
three ways:

1. During power up, once the PLL has locked to the

reference clock provided on the REFCLK pins, the
LOCKDET will go active and initialize the FIFO.

2. When RSTB goes active, the entire chip is reset.

This causes the PLL to go out of lock and thus the
LOCKDET goes inactive. When the PLL reac-
quires the lock, the LOCKDET goes active and
initializes the FIFO. Note: PCLK is held reset
when RSTB is active.

3. The user can also initialize the FIFO by raising

PHINIT.

During the normal running operation, the incoming
data is passed from the PICLK timing domain to the
internally generated divide by 16 clock timing do-
main. Although the frequency of PICLK and the

internally generated clock is the same, their phase
relationship is arbitrary. To prevent errors caused by
short setup or hold times between the two timing
domains, the timing generator circuitry monitors the
phase relationship between PICLK and the internally
generated clock. When a potential setup or hold time
violation is detected, the phase error goes High.
When PHERR conditions occur, PHINIT should be
activated to recenter the FIFO (at least 2 PCLK peri-
ods). This can be done by connecting PHERR to
PHINIT. When realignment occurs up to 10 bytes of
data will be lost. The user can also take in the
PHERR signal, process it and send an output to
PHINIT in such a way that idle bytes are lost during
the realignment process. PHERR will go inactive
when the realignment is complete.

RECEIVER OPERATION

The S3059 receiver chip provides the first stage of
the digital processing of a receive SONET STS-48/
STS-24/STS-12/STS-3/GBE bit-serial stream. It con-
verts the bit-serial 2.488 Gbps, 1.244 Gbps, 622.08
Mbps, 155.52 Mbps, 1.25 Gbps data stream into a
16-bit parallel data format. A loopback mode is pro-
vided for diagnostic loopback (transmitter to
receiver). A line loopback (receiver to transmitter) is
also provided. Both line and local loopback modes
can be active at the same time.

Serial-to-Parallel Converter

The serial-to-parallel converter consists of two 16-bit
registers. The first is a serial-in, parallel-out shift reg-
ister, which performs the serial-to-parallel conversion
clocked by the clock recovery block. On the falling
edge of the POCLK, the data in the parallel register
is transferred to an output parallel register which
drives POUTP/N[15:0].

OTHER OPERATING MODES

Diagnostic Loopback

When the Diagnostic Loopback Enable (DLEB) input
is active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for
diagnostic purposes. The differential serial output
data from the transmitter is routed to the serial-to-
parallel block in place of the normal Receive Serial
Data (RSD). TSD/TSCLK outputs are active. DLEB
takes precedence over SDLVPECL and SDLVTTL.

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