1
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
October 23, 2000 / Revision A
BiCMOS PECL CLOCK GENERATOR
DEVICE
SPECIFICATION
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
S3076
FEATURES
SiGe BiCMOS technology
Complies with Bellcore and ITU-T specifica-
tions for jitter tolerance, jitter transfer and
jitter generation
On-chip high frequency PLL with internal
loop filter for clock recovery
Supports clock recovery for:
OC-48 (2488.32 Mbps) (with FEC)
Fibre Channel (2125 Mbps) (with FEC)
OC-24 (1244.16 Mbps) (with FEC)
Gigabit Ethernet (1250 Mbps) (with FEC)
Fibre Channel (1062.5 Mbps) (with FEC)
OC-12 (622.08 Mbps) (with FEC)
OC-3 (155.52 Mbps) (with FEC) NRZ data
Selectable reference frequencies
19.44 MHz or 155.52 MHz
(or equivalent Fibre Channel/
Gigabit Ethernet frequencies)
Lock detect--monitors frequency of
incoming data
Low-jitter serial interface
+3.3 V supply
Compact 48 pin TQFP TEP package
Typical power 620 mW
Available in Die form also
GENERAL DESCRIPTION
The function of the S3076 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3076 is implemented using
AMCC's proven Phase Locked Loop (PLL) technology.
Figure 1 shows a typical network application.
The S3076 receives an OC-48, OC-24, OC-12, OC-3,
Fibre Channel or Gigabit Ethernet scrambled NRZ sig-
nal with FEC capability up to 8 bytes per 255-byte
block and recovers the clock from the data. The chip
outputs a differential bit clock and retimed data.
The S3076 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
Figure 1. System Block Diagram
Network Interface
Processor
Network Interface
Processor
S3057
S3057
OTX
ORX
OTX
ORX
16
16
16
16
S3076
S3076
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S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
October 23, 2000 / Revision A
S3076 OVERVIEW
The S3076 supports clock recovery for the OC-48,
Fibre Channel (2125 Mbps), OC-24, Gigabit
Ethernet, Fibre Channel (1062.5 Mbps), OC-12 or
OC-3 data rate with FEC capabilty up to 8 bytes per
255-byte block. Differential serial data is input to the
chip at the specified rate, and clock recovery is per-
formed on the incoming data stream. An external os-
cillator is required to minimize the PLL lock time, and
provide a stable output clock source in the absence of
serial input data. Retimed data and clock are output
from the S3076.
Figure 2. S3076 Functional Block Diagram
2
SERCLKOP/N
LOCKDET
SERDATOP/N
REFCLKP/N
TESTCLK
LCKREFN
SERDATIP/N
LOOP
FILTER
VCO
CLOCK
DIVIDER
PHASE DETECTOR
LOCK
DETECTOR
SDN
CAP 1,2
RATESEL[1:0]
REFSEL
TESTEN
RST
BYPASS
2
TESTOUT
REFCMP
Suggested Interface Devices
Sumitomo
OC-48 Optical Receiver
AMCC S3057
OC-48 Transceiver
3
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
October 23, 2000 / Revision A
S3076 FUNCTIONAL DESCRIPTION
The S3076 clock recovery device performs the clock
recovery function for SONET OC-48, Fibre Channel
(2125 Mbps), OC-24, Gigabit Ethernet, Fibre
Channel (1062.5 Mbps), OC-12 or OC-3 serial data
links with FEC capabilty up to 8 bytes per 255-byte
block. The chip extracts the clock from the serial data
inputs and provides retimed clock and data outputs.
A 155.52/19.44 MHz (156.25/19.53 MHz for Gigabit
Ethernet and 132.81/16.60 MHz for Fibre Channel)
reference clock is required for phase locked loop
start up and proper operation under loss of signal
conditions. An integral prescaler and phase locked
loop circuit is used to multiply this reference to the
nominal bit rate. The input data rate is selected by
the RATESEL inputs. (See Table 1.)
Clock Recovery
Clock recovery, as shown in the block diagram in
Figure 2, generates a clock that is at the same fre-
quency as the incoming data bit rate at the serial
data input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.
The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.
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Table 1. Data Rate Select
Table 2. Reference Frequency Select
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal varies by a value greater than
that stated in Table 7 with respect to REFCLKP/N,
the PLL will be declared out of lock, and the PLL will
lock to the reference clock. The assertion of SDN will
also cause an out of lock condition.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET
data signal.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 3.
Lock Detect
The S3076 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss of signal or loss of lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than that stated in
Table 7, the PLL will be declared out of lock. The lock
detect circuit will poll the input data stream in an attempt
to reacquire lock to data. If the recovered clock fre-
quency is determined to be within that stated in
Table 7, the PLL will be declared in lock and the lock
detect output will go active. The assertion of SDN will
also cause an out of lock condition.
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S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
October 23, 2000 / Revision A
Figure 3. Input Jitter Tolerance Specification
Figure 4. Jitter Transfer Specification
1. Bellcore Specifications: GR-253- CORE, Issue 2, December 1995.
2. ITU-T Recommendations: G.958.
3. Not specified in GR-253 or G.958.
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Sinusodal
Input Jitter
Amplitude
(UI p-p)
Frequency
SONET JITTER CHARACTERISTICS
Performance
The S3076 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
Bellcore Specifications: GR-253-CORE, Issue 2, De-
cember 1995 and ITU-T Recommendations: G.958
document, when used as specified.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. SONET input jitter
tolerance requirements are shown in Figure 3.
Jitter Transfer
The jitter transfer function is defined as the ratio of
jitter on the output OC-N/STS-N signal to the jitter
applied on the input OC-N/STS-N signal versus fre-
quency. Jitter transfer requirements are shown in Fig-
ure 4. The measurement condition is that input
sinusoidal jitter up to the mask level in Figure 4 be
applied.
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed the value specified in Table 7. when
a serial data input with no jitter is presented to the
serial data inputs. (See Table 7.)
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5
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
October 23, 2000 / Revision A
FIBRE CHANNEL
JITTER CHARACTERISTICS
Performance
The S3076 PLL complies with the jitter specifications
proposed for Fibre Channel equipment defined by the
fibre channel methodology for Jitter specification.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. Fibre Channel input
j i t t e r t o l e r a n c e r e q u i r e m e n t s a r e s h o w n i n
Table 3.
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed the value specified in Table 4 when
a serial data input with no jitter is presented to the
serial data inputs.
SYSTEM
STORAGE
DISK DRIVE
SERDES
SERDES
BACKPLANE
PBC
REPEAETERS
CABLES
CONNECTORS
Componet Receiver Node =
R
SYSTEM
HOST ADAPTOR
T
= Component Transmitter Node
Figure 5. Fibre Channel System Node Definition
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Table 3. Input Jitter Tolerance Specification at
node
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Table 4. Total Jitter Generation Specification at
node
T
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