Part Number S3078
Revision NC - December 22, 2000
1
S3078
Multi-Rate Limiting Amplifier and Clock Recovery Unit
DEVICE SPECIFICATION
Features
SiGe BiCMOS Technology
+3.3 V Power Supply
Integrated Limiting Amplifier
No Degradation in Jitter Tolerance down to
5 mV Input
Loss-of-Signal Detection
Supports Clock Recovery for:
OC-48 (2488.32 Mbps) with FEC
OC-24 (1244.16 Mbps) with FEC
OC-12 (622.08 Mbps) with FEC
OC-3 (155.52 Mbps) with FEC NRZ data
Gigabit Ethernet (GBE) (1250 Mbps) with FEC
Fibre Channel (FC) (1062.5 Mbps) with FEC
Fibre Channel (FC) (2125 Mbps) with FEC
Lock Detect monitors frequency of
incoming data
Selectable reference frequencies
155.52 MHz 166.62 MHz or
19.44 MHz 20.83 MHz
Typical power 730 mW
81 Pin PBGA package and Die
General Description
The S3078 is a 3.3 V combined limiting amplifier and
Clock Recovery Unit (CRU) for multi-rate applications.
Figure 1 shows a typical network application.
The internal limiting amplifier provides a voltage limited
signal into the CRU for inputs down to 5 mV. It has a
Loss-of-Signal (LOS) output, which can be programmed
to assert with input levels between 25 mVp-p and 60
mVp-p. There is also an offset correction function that
reduces pulse-width distortion.
The CRU is implemented using AMCC's proven on-
chip Phase Locked Loop (PLL) technology, and it can
lock onto OC-48, OC-24, OC-12, GBE, FC, or OC-3
scrambled NRZ signal with FEC capability up to 8
bytes per 255-byte block, and recovers the clock from
the data. It consists of a phase detector, a loop filter,
and a Voltage Controlled Oscillator (VCO). The phase
detector compares the phase relationship between the
VCO output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input into the VCO
whose frequency is varied by this voltage.
Figure 1. System Block Diagram
Network Interface
Processor
S3057
S3057
Network Interface
Processor
S3049
S3049
S3078
S3078
S3060
S3060
2
S3078 Multi-Rate Limiting Amplifier and
Clock Recovery Unit
Revision NC - December 22, 2000
D EVIC E SPEC IFIC ATIO N
FUNCTIONAL DESCRIPTION
The block diagram in Figure 2 shows the architecture
of the S3078. It has a limiting amplifier integrated with
a Clock Recovery Unit (CRU).
Limiting Amplifier
The limiting amplifier at the input of the device quan-
tize s th e signa l, a nd ou tpu ts a voltag e-limite d
waveform over a 62 dB input dynamic range. It pro-
vides 43 dB of linear gain (in three linear gain stages)
followed by up to 15 dB of quantized gain (in the digital
buffer), before it is presented into the phase detector
of the PLL. This allows the device to operate with
inputs down to 5 mV, differential, with no degradation
in jitter tolerance.
The S3078 provides an input offset correction function
that effectively reduces the offset voltage to negligible
levels. An external capacitor, CAZ, should be added
between CAZ1 and CAZ2 to compensate the offset
correction loop.
Loss-Of-Signal Function
The limiting amplifier incorporates a chatter-free loss-
of-signal function, which is used to detect that the
input signal has dropped below the level necessary for
acceptable bit error rate performance. The loss-of-sig-
nal function is implemented with a rectifying peak
detector, which samples the signal at the output of the
first gain stage.
The peak detector has a filter to slow its response to the
peaks. Nominal response time is 0.01
s, but this can
be increased by adding an external cap, CLD, to V
CC
.
The output from the peak detector, V
OUT
, is compared
against a threshold level V
TH
, which is externally con-
trolled by the input voltage V
LOS
, where V
LOS
is
referred to V
CC
. LOS is asserted if V
OUT
falls below
V
TH
. Figure 9 shows the V
TH
as a function of V
LOS
.
Level-detect hysteresis ensures chatter-free LOS out-
put when the input signal level is close to the LOS
threshold. The hysteresis for any programmed loss-of-
signal level is nominally 5 dB.
Figure 2. Functional Block Diagram
Loop
Filter
VCO
Lock
Detector
Phase Detector
Clock
Divider
REFCLKP/N
TESTCLK
RATESEL[1:0]
LCKREFN
REFSEL
SDN
BYPASS
CAP2
2
2
SERCLKOP/N
LOCKDET
SERDATOP/N
REFCMP
DINP
DINN
Peak
Detect
-
+
V
TH
OFFSET
CORRECTION
LOOP
Linear
GS1
Linear
Gs2
Linear
GS3
Digital
Buffer
V
LOS
CAZ1
CLD
LOSP
LOSN
CAP1
V
OUT
V
CC
CAZ2
V
CC
VLOS
V
CC
0.1
F
RST
TESTEN
TESTOUT
+
3
S3078 Multi-Rate Limiting Amplifier and
Clock Recovery Unit
Revision NC - December 22, 2000
D EVIC E SPEC IFIC ATIO N
Clock Recovery Unit
The S3078 supports clock recovery for OC-48, OC-24,
Gigabit Ethernet, Fibre Channel, OC-12, and OC-3
data rates with FEC capability up to 8 bytes per 255-
byte block.
The clock recovery block generates a clock that is at
the same frequency as the incoming data bit rate at
the output of the limiting amplifier. The clock is phase
aligned by a PLL so that it samples the data in the cen-
ter of the data eye pattern.
A phase/frequency discriminator compares the phase
relationship between the edge transitions of the data
and those of the generated clock. Output pulses from
the discriminator indicate the required direction of
phase corrections. These pulses are smoothed by an
integral loop filter. The output of the loop filter controls
the frequency of the Voltage Controlled Oscillator
(VCO), which generates the recovered clock.
Frequency stability without incoming data is guaran-
teed by an alternate reference clock input (REFCLK)
that the PLL locks onto when data is lost. If the fre-
quency of the incoming signal varies by greater than
that stated in Table 5 with respect to REFCLKP/N, the
PLL will be declared out of lock, and the PLL will lock
to the reference clock. The assertion of SDN will also
cause an out of lock condition.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET data
signal. The total loop dynamics of the clock recovery
PLL yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 6.
Lock Detect
The S3078 contains a lock detect circuit which moni-
tors the integrity of the serial data inputs. If the
recovered clock frequency deviates from the local ref-
erence clock frequency by more than that stated in
Table 5, the PLL will be declared out of lock (the
LOCKDET output will go inactive) and it will be forced
to lock to the local reference clock. This will maintain
the correct frequency of the recovered clock output
under loss of signal or loss of lock conditions.
The lock detect circuit will poll the input data stream in
an attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within that stated
in Table 5, the PLL will be forced to lock to the data
and the LOCKDET output will go active.
The assertion of SDN will also cause an out of lock
condition.
4
S3078 Multi-Rate Limiting Amplifier and
Clock Recovery Unit
Revision NC - December 22, 2000
D EVIC E SPEC IFIC ATIO N
Table 1. Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin#
Description
DINP
DINN
Analog
I
J4
J3
Positive/Negative data inputs.
CLD
Analog
I
J6
A capacitor to V
CC
can be added here to set the LOS
circuit response time. It can be left open for minimum
response time. See Design Procedures to determine the
desired capacitance.
VLOS
DC
I
G5
Power Detect/LOS level set. This input is to program the
required threshold level for LOS assertion. If left open, the
threshold will be set to the minimum level. The value of
V
LOS
can be determined using the plot in Figure 9. This pin
should be bypassed to VCC through a 0.1
F capacitor.
CAZ1
CAZ2
Analog
E1
D1
A 10 nF offset-correction loop compensation capacitor
should be connected between these two pins. (See Design
Procedures.)
LOSP
LVTTL
O
H7
Loss-of-Signal Detect. This pin is asserted High when the
power drops below the LOS threshold, set by V
LOS
.
LOSN
LVTTL
O
J7
Loss-of-Signal Detect. This pin is asserted Low when the
power drops below the LOS threshold, set by V
LOS
.
BYPASS
LVTTL
I
C3
Bypass. Active High. Used to bypass the PLL. It allows
transmission of the data without clock recovery.
SDN
Single-
Ended
LVPECL
I
B2
Signal Detect. Active Low. A single-ended 10K PECL input
to be driven by the external optical receiver module to indi-
cate a loss of received optical power. When SDN is inac-
tive, the input data will be internally forced to a constant
zero, and the PLL will be forced to lock to the REFCLK
inputs. When SDN is active, data on the DINP/N pins will
be processed normally. If not used leave open.
REFCLKP
REFCLKN
Internally
Biased
Diff.
LVPECL
I
F9
G9
Reference Clock. 155.52/19.44 MHz input used to estab-
lish the initial operating frequency of the clock recovery
PLL and also used as a standby clock in the absence of
data, during reset or when SDN is inactive.
CAP1
CAP2
Analog
A5
B5
PLL Loop FIlter Capacitor. The loop filter capacitor and
resistors are connected to these pins. See Figure 14.
LCKREFN
LVTTL
I
E7
Lock to Reference. Active Low. When active, the serial
clock output will be forced to lock to the local reference
clock input [REFCLK].
RATESEL0
RATESEL1
LVTTL
I
E6
D6
Rate Select. Selects the operating mode. See Table 16. If
left open, they will default to a (Logic "1") High state.
REFSEL
LVTTL
I
G8
Reference Clock Select. Selects the reference frequency.
See Table 17.
SERDATOP
SERDATON
Diff.
CML
O
C9
D9
Serial Data Out. This signal is the data output updated on
the falling edge of Serial Clock Out (SERCLKOP).
SERCLKOP
SERCLKON
Diff.
CML
O
A8
A9
Serial Clock Out. This signal is phase aligned with Serial
Data Out (SERDATOP/N). See Figure 8.
5
S3078 Multi-Rate Limiting Amplifier and
Clock Recovery Unit
Revision NC - December 22, 2000
D EVIC E SPEC IFIC ATIO N
LOCKDET
LVTTL
O
H8
Lock Detect. Clock recovery indicator. When high, the
internal clock recovery unit has locked onto the incoming
data stream. LOCKDET is an asynchronous output.
TESTEN
LVTTL
I
B3
Test Enable. Active High input used for production test.
This pin should be grounded for normal operation.
TESTCLK
LVTTL
I
H9
Test clock. Used for production test. This pin should be
grounded for normal operation.
RST
LVTTL
I
F8
Reset. Active High input used for production test. This pin
should be grounded for normal operation.
TESTOUT
LVPECL
O
E8
Test Output. Leave open for normal operation.
VCC1
Power
A1, B1
LA (Limiting Amplifier) supply #1
VEE1
Ground
C2
LA (Limiting Amplifier) ground #1
VCC2
Power
C1
LA (Limiting Amplifier) supply #2
VEE2
Ground
D2
LA (Limiting Amplifier) ground #2
VCC3
Power
H6
LA (Limiting Amplifier) supply #3
VEE3
Ground
G6
LA (Limiting Amplifier) ground #3
VCC4
Power
F1
LA (Limiting Amplifier) supply #4
VEE4
Ground
F2, G1
LA (Limiting Amplifier) ground #4
VCC5
Power
H1, H2, J1
LA (Limiting Amplifier) supply #5
VEE5
Ground
G3, G4, H3, H4, H5,
J2, J5
LA (Limiting Amplifier) ground #5
VEEX
Ground
C4, C5, C6, D3, D4,
E3, E4, F3, F4
Ground
VCC7
Power
A2
CRU digital supply #1
VEE7
Ground
A3
CRU digital ground #1
VCC8
Power
E9
CRU digital supply #2
VEEG
Ground
D5, E5, F5
CRU digital ground #2
VCC9
Power
J9
CRU low speed digital circuit supply
VCC10
Power
A4
CRU Analog supply #1
VEE10
Ground
B4
CRU Analog ground #1
VCC11
Power
A6
CRU Analog supply #2
VEE11
Ground
B6
CRU Analog ground #2
VCC13
Power
C8
Data output buffer supply
VEE13
Ground
C7
Data output buffer ground
VCC14
Power
B7, B8
Clock output buffer supply
Table 1. Pin Assignment and Descriptions (Continued)
Pin Name
Level
I/O
Pin#
Description
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