AMCC
S4801
Amazon Device Specification
Revision NC
July 21, 2000
Features
Part Number S4801
Revision NC - September 2000
General Description
AMAZON
STS-48c POS/ATM SONET MAPPER
S4801 Block Diagram
AMCC
Device Specification Information - The information con-
tained in this document is about a product in its fully tested
and characterized phase. All features described herein are
supported. Contact AMCC for updates to this document and
the latest product status.
DEVICE SPECIFICATION
Processes SONET/SDH STS-48c/(STM-16/AU-4-
16c) data streams with full duplex mapping of ATM
cells or packets (PPP or LAPS) into SONET/SDH
payloads.
Terminates and generates SONET/SDH section, line,
and path layers, with transport/section E1, E2, F1 and
DCC overhead serial interfaces in both transmit and
receive directions.
Provides a 16-bit parallel line-side interface operating
at 155 MHz, and a 64/32-bit parallel system-side
interface, operating at 50/100 MHz.
Selectable scrambling/descrambling (1+X
6
+X
7
) of
SONET/SDH frame.
Selectable self-synchronous scramblers (before or
after the ATM/HDLC processors) implementing (X
43
+1) polynomial for ATM or Packet over SONET appli-
cations.
Generic 8-bit microprocessor interface for configura-
tion, control, and status monitoring.
Provides an 8-bit General Purpose I/O (GPIO) regis-
ter and associated hardware interface pins.
Provides an IEEE 1149.1 JTAG (Boundary Scan ) test
port.
Packaged in a 360 CBGA
Implemented in .35 micron, 3.3V process technology.
The S4801 is a highly-integrated VLSI device that pro-
vides full-duplex mapping of PPP/LAPS encapsulated
packets or ATM cells into SONET/SDH payloads.
The S4801 provides full section, line, and path overhead
processing and supports framing, scrambling/descram-
bling, alarm signal insertion/detection, and bit inter-
leaved parity (B1/B2/B3) processing.
The S4801 is standards compliant with Bellcore
GR-253, ITU G.707, ANSI T1.105 -1995, IETF RFCs
1619/1661/1662/2615 (PPP) and ITU-T COM
7-224-E/D307 (LAPS recommendation) protocols.
A general purpose 8-bit microprocessor interface is pro-
vided for control, and monitoring. The interface supports
both Intel and Motorola type microprocessors, and is
capable of operating in either an interrupt driven or
polled-mode configurations.
Applications
ATM switches
Packet over SONET Routers and Switches
SONET/SDH Add Drop Multiplexers, Terminal
Multiplexers and Digital Cross Connects
Test equipment
Concentrators
U
T
OP
IA
-
3
o
r
F
l
exB
U
S
-
3
TM
INT
E
RF
A
C
E
TX_SYS_DAT[63:0]
TX_CLK
TX_PRTY
TX_ENB
TX_SOC/P
TX_CLAV/PA
RX_SYS_DAT[63:0]
RX_CLK
RX_PRTY
RX_ENB
RX_SOC/P
RX_CLAV/PA
RX ATM/HDLC
(PPP/LAPS)
PROC
POINTER
INTERPRET
POH
MONITOR
TOH EXTRACT
TOH
MONITOR
RX
FRAMER
L
I
NE S
I
DE
INT
E
RF
ACE
TX
FRAMER
TOH INSERT
SPE/VC
GENERATE
T
X
S
DCCDA
T
A
T
X
SDCCCL
K
T
X
L
DCCDA
T
A
T
X
L
DCCC
L
K
TX
E1
E2
F1
F
R
AM
E
TXE
1
E2
F1
D
A
T
RXS
DCCDA
T
A
RXS
DCCCL
K
RXL
DCCDA
T
A
RXL
DCCCL
K
RXE
1
E2
F1
F
R
AM
E
R
X
E1
E2
F1
D
A
T
RX_RVAL
RX_VBYTE[2:0]
RX_EOP
RX_ERR
TX_VBYTE[2:0]
TX_EOP
TX_ERR
D[7
:
0
]
A
DDR[1
1
:0
]
CSN
RDB
(
D
S
B
)
WRB(
R
W
B
)
R
D
YB(
DT
ACK
B
)
BUSM
O
D
E
INT
B
MICROPROCESSOR I/F
JTAG PORT
GPIO/LED REG
TD
O
TD
I
TC
K
TMS
TR
S
T
B
GP
IO[7:0]
TX_DATA[15:0]
TX_SONETCLK
TX_FRAME_IN
RX_DATA[15:0]
RX_SONETCLK
RX_FRAME_IN
T
X
8K
CLK
RS
T
B
A
PS_
I
N
T
B
TS
_E
N
RX_LOS_IN
RX
FIFO
DE-SCRMBL
(X
43
+ 1)
RX ATM/HDLC
(PPP/LAPS)
CNTRS
TX
FIFO
DE-SCRMBL
(X
43
+ 1)
SCRMBL
(X
43
+ 1)
TX ATM/HDLC
SCRMBL
(X
43
+ 1)
RX_ALRM_OUT
RX_CLK_OUT
TX_SONETCLKOUT
(PPP/LAPS)
PROC
S4801 STS-48c POS/ATM SONET Mapper
PRELIMINARY PRODUCT DATASHEET
Revision NC - September 2000
AMCC
200 Brickstone Square, Andover, MA 01810 Ph: (978) 623-0009 Fax:(978) 623-0024
DEVICE SPECIFICATION
Overview and Applications
SONET Processing
The S4801 implements SONET/SDH processing and
full-duplex ATM/POS mapping functions for
STS-48/STM-16 data streams. It supports a single
STS-48c/AU-4-16c signal within an STS-48/STM-16. A
TOH/SOH interface provides direct add/drop capability
for E1, E2, F1, and both Section and Line DCC chan-
nels. The S4801 also includes a clear channel mode that
enables the direct transmission of system payload from
the system interface to the line-side interface.
On the transmit side the S4801 generates section, line,
and path overhead. It performs framing pattern insertion
(A1, A2), scrambling, alarm signal insertion, and gener-
ates section, line and path Bit Interleaved Parity
(B1/B2/B3) for far-end performance monitoring.
On the receive side the S4801 processes section, line,
and path overhead. It performs framing (A1, A2),
descrambling, alarm detection, Pointer Interpretation, Bit
Interleaved Parity monitoring (B1/B2/B3), and error
count accumulation for performance monitoring.
ATM Processing
When configured for ATM cell processing, the S4801's
transmit ATM processor will perform all necessary cell
encapsulation including HEC generation, cell payload
scrambling (X
43
+1) and idle cell insertion to adapt the
cell rate to the SPE. When receiving data from the line
side, it performs cell delineation, Rx header error correc-
tion/detection, descrambling, and detects & deletes idle
cells.
Packet/HDLC Processing
When configured for POS mode, the S4801's transmit
HDLC processor provides the insertion of HDLC framed
PPP/LAPS packets into the STS SPE. It will perform
packet framing, inter-frame fill and Tx FIFO error recov-
ery. In addition, it optionally performs scrambling
(X
43
+1), either pre or post the HDLC processor, per-
forms transparency processing as required by RFC
1662/ITU-T COM7-D307 and will optionally generate a
16/32 bit FCS.
The receive HDLC processor provides for the extraction
of PPP/LAPS packets from HDLC frames, transparency
removal, de-scrambling (if enabled), FCS error check-
ing, and optionally deletes the HDLC address and con-
trol fields.
Line-side Interface
On the line-side, the S4801 supports a 16-bit parallel
interface, operating at 155MHz. The device is typically
connected to parallel-to-serial / serial-to-parallel convert-
ers, which are in turn connected to an electrical-to-opti-
cal converter for interfacing to the fiber optic interface.
(See figure below.)
System Interface
The S4801 supports a 64/32 bit, 50/100 MHz system
interface. When operating in ATM mode, the S4801 sup-
ports the 32-bit, 100 MHz, Utopia Level-3 interface, as
well as a 64-bit, 50 MHz extension of the Utopia Level-3
specification. When operating in Packet over SONET
mode, the S4801 supports a 64/32-bit, 50/100 MHz,
FlexBUS-3
TM
interface.
TYPICAL APPLICATIONS: S4801 in 2.488 Mb/s ATM or POS System
TX_DATA[15:0]
TX_SONETCLK
RX_SONETCLK
RX_DATA[15:0]
Microprocessor
Control
Control
Reference
Clock
Fiber Optic
Transceiver
SONET
Line Side
Interface
RX_LOS
S4801
AMCC
Addr
Data
8
12
TX_CLK
TX_SYS_DAT[63:0]
RX_CLK
RX_SYS_DAT[63:0]
System Interface
TOH Insertion
and Extraction
IP Router or ATM Switch
OR
Multi
Channel
Link Layer
Device
IP ROUTER
Switching/
Routing
Logic
HP / Lucent
[31:0]
[31:0]
OC-48
Line Interface
Sumitomo
FlexBUS-3
TM
Recovery
16:1 P/S
SONET
Transmitter
SONET
Receiver
1:16 S/P
S3044
S3064
S3040
S3050
CLK
Ser
RxD
Ser
RxCLK
S3043
S3083
TX_SONETCLKOUT
Ser RxD
AMCC - Confidential and Proprietary v
Table of Contents
Revision NC - September 2000
DEVICE SPECIFICATION
S4808PBI STS-48c POS/ATM SONET MAPPER
1.0 Applicable Documents ................................................................................................................. 11
2.0 Pin Assignments and Descriptions ............................................................................................ 12
2.1 Pin Descriptions ........................................................................................................................ 12
Table 1: Line Side SONET Interface ....................................................................................... 12
Table 2: UTOPIA3/Flexbus-3 System Interface ....................................................................... 15
Table 3: Microprocessor Interface ............................................................................................ 25
Table 4: GPIO/LED/TOH Interface ........................................................................................... 27
Table 5: Test Interface .............................................................................................................. 29
Table 6: Power, Ground, and Reserved Pins ........................................................................... 29
3.0 Mechanical Packaging information ............................................................................................. 31
Table 7: Mechanical Specifications .......................................................................................... 33
Table 8: Thermal Performance ................................................................................................. 33
Table 9: Ordering Information ................................................................................................... 33
4.0 Functional Descriptions ............................................................................................................... 34
4.1 Common Conventions .............................................................................................................. 34
4.2 Monitors and Control Interface .................................................................................................. 34
4.3 Configuration ............................................................................................................................. 35
4.3.1 TX Configuration ..................................................................................................................... 35
4.3.2 RX Configuration..................................................................................................................... 35
4.4 SONET/SDH Processing .......................................................................................................... 35
4.4.1 Receive SONET/SDH Processing .......................................................................................... 35
4.4.2 Transmit SONET/SDH Processing ......................................................................................... 36
4.5 HDLC/ATM Processing ............................................................................................................. 37
4.5.1 Receive HDLC Processor ....................................................................................................... 37
4.5.2 Receive ATM Processor ......................................................................................................... 39
4.5.3 Transmit HDLC Processor ...................................................................................................... 39
4.5.4 Transmit ATM Processor ........................................................................................................ 40
4.6 FCS Polynomials ...................................................................................................................... 40
5.0 Processing of Data in the Transmit Direction ............................................................................ 42
5.1 Transmit FIFO Interface ............................................................................................................ 42
5.1.1 Transmit Data Parity Check .................................................................................................... 42
5.1.2 Transmit FIFO......................................................................................................................... 42
5.1.3 POS Errored Packet Handling ................................................................................................ 42
5.2 Transmit HDLC Processing ...................................................................................................... 43
5.2.1 Transmit Valid Packet Count .................................................................................................. 43
5.2.2 Pre-HDLC Scrambling ............................................................................................................ 43
5.2.3 Encapsulation of Packets in HDLC Frame.............................................................................. 44
5.2.4 Address and Control Fields..................................................................................................... 44
5.2.5 Frame Check Sequence (FCS) Field...................................................................................... 44
5.2.6 Transparency .......................................................................................................................... 45
5.2.7 SPE Creation .......................................................................................................................... 45
vi AMCC - Confidential and Proprietary
Table of Contents (continued)
Revision NC - September 2000
DEVICE SPECIFICATION
S4808PBI STS-48c POS/ATM SONET MAPPER
Table 10: Octet Values Handled by Transparency Processing ................................................ 45
5.3 Transmit ATM Processing ......................................................................................................... 46
5.3.1 Transmit Data HEC Check...................................................................................................... 46
5.3.2 Transmit Valid Cell Count ....................................................................................................... 47
5.3.3 SPE Payload Creation ............................................................................................................ 47
Table 11: Pattern for Default Idle Cell ...................................................................................... 47
Table 12: ATM Cell Header Format .......................................................................................... 47
5.3.4 Header Error Control (HEC) Sequence Generation................................................................ 48
5.4 Scrambling ................................................................................................................................ 48
5.4.1 ATM Scrambler Operation ...................................................................................................... 48
5.4.2 HDLC Scrambler Operation .................................................................................................... 48
5.4.3 Direct SPE Mapping Scrambler Operation ............................................................................. 48
5.5 SPE/VC Generation .................................................................................................................. 48
5.5.1 SPE/VC Structure ................................................................................................................... 49
5.5.2 POH ........................................................................................................................................ 49
5.6 SONET/SDH Frame Generation ............................................................................................... 50
Table 13: Path RDI Bit Values .................................................................................................. 50
5.6.1 Frame Alignment..................................................................................................................... 51
5.6.2 TOH/SOH Generation............................................................................................................. 52
Table 14: STS-48/STM-16 TOH/SOH ...................................................................................... 52
5.6.3 Scrambling .............................................................................................................................. 55
6.0 Processing of Data in the Receive Direction ............................................................................. 56
6.1 T-to-R Loopback, LOC, and LOS .............................................................................................. 56
6.1.1 T-to-R Loopback ..................................................................................................................... 56
6.1.2 LOC......................................................................................................................................... 56
6.1.3 LOS......................................................................................................................................... 56
6.2 STS-48/STM-16 Framer ........................................................................................................... 56
6.2.1 Framer Operation.................................................................................................................... 57
6.2.2 Out-of-Frame Data Disable..................................................................................................... 57
6.2.3 Descrambling .......................................................................................................................... 57
6.2.4 B1 Monitor............................................................................................................................... 57
6.3 Transport Overhead Monitoring ................................................................................................ 57
6.3.1 J0 Monitoring .......................................................................................................................... 57
6.3.2 BIP-384 (B2) Checking ........................................................................................................... 58
6.3.3 K1K2 Monitoring ..................................................................................................................... 59
6.3.4 AIS-L Data Disable ................................................................................................................. 59
Table 15: STS-48/STM-16 Signal Fail and the Signal Degrade Provisioning Values .............. 59
6.3.5 S1 Monitoring.......................................................................................................................... 60
6.3.6 M1 Monitoring ......................................................................................................................... 60
6.3.7 External Alarm Signal ............................................................................................................. 60
6.4 Transport Overhead Drop ......................................................................................................... 60
6.4.1 Orderwire (E1 and E2) and Section User Channel (F1) ......................................................... 61
6.4.2 Data Communications Channels, DCC, (D1-D12).................................................................. 61
6.5 Pointer State Determination ...................................................................................................... 61
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