Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 1
May 17, 1994
BiCMOS PECL CLOCK GENERATOR
EVALUATION BOARD DESCRIPTION
The S6003 Evaluation Board allows demonstration
of AMCC's S3014 SONET clock synthesis and re-
covery unit. This data sheet provides information on
board contents and layout. It should be used in con-
junction with the S3014 data sheet, which contains
full technical details on chip operation.
Figure 1 depicts the layout of the evaluation board,
showing the location of connectors and components.
Power is supplied to the board from external raw
supplies connected through the on-board power con-
nections. Coaxial SMA connectors are used for serial
data link and external reference clock connections.
Figure 1. S6003 Board Layout
SERDATON
SERDATOP
S3014
SERCLKOP
XTAL
SERDATIP
SERCLKON
REFCKINP
REFCKINN
SERDATIN
1
2
3
4
5
6
SEL0
SEL1
SEL2
LOS
RST
TSTCLKEN
LOCKDET
VCC
GND
VEE
JP1
JP2
JP3
JP4
Clean-up
capacitor
(bottom
of
board)
EVALUATION BOARD
S3014 EVALUATION BOARD
S6003
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 2
May 17, 1994
Figure 2. Clock Jumper Configurations
Table 1. Power Connection
Recommended Operating Conditions
Power Supply Nominal Input Voltage
Function
VCC
5 V
TTL Supply
Ground
0 V
VEE
5 V
PLL & Core Supply
SMA Connectors
Eight coaxial SMA connectors are provided for the
differential serial data signals and the clock input/
output signals. All connectors, components, and con-
trols are labeled on the board by name. (See Figure
1 for locations.)
Serial Data In (SERDATIP/N). Differential ECL. When
the S3014 is used in the Clock Recovery Mode, the
clock is recovered from the transitions on these inputs.
Reference Clock [REFCKINP/N]. Differential ECL.
Input used as the reference for the internal bit clock
frequency synthesizer.
Serial Clock Out [SERCLKOP/N]. Differential ECL.
Output signal that is phase-aligned with Serial Data
Out in the Clock Recovery Mode.
Serial Data Out [SERDATOP/N]. Differential ECL. In
the Clock Recovery Mode, this signal is the delayed
version of the incoming data stream, phase aligned
with Serial Clock Out.
Note: All ECL outputs must be terminated 50
to -2V
off-chip. When connecting the serial clock and serial
data outputs to test equipment with a 50
to GND
termination, an ECL terminator should be used to
match the 50
to -2V termination requirement of the
S6003 with the 50
to GND termination of the test
equipment.
CRYSTAL REFERENCES
A 19.44, 51.84, or 155.52 MHz differential ECL crys-
tal oscillator can be used for the reference clock.
One 19.44 MHz crystal is provided. If a different ref-
erence frequency is needed, AMCC can recommend
crystal vendors.
ELECTRICAL CONNECTIONS
Power Connections
Connections are provided on the board for ground,
the TTL power supply (VCC), and the core and PLL
supply (VEE). Refer to Table 1 for recommended op-
erating conditions.
REFCKINN
JP4
EXTERNAL CLOCK
REFCKINN
JP4
CRYSTAL
Alternatively, an external reference clock can be pro-
vided by configuring the JP4 jumpers located between
the REFCKINN and REFCKINP connectors as shown
in Figure 2, and connecting a differential clock to the
appropriate SMA connectors.
The desired input frequency is selected using the
SEL0 and SEL1 switches (see Table 2).
LED
The single on-board LED provides a display for the
Lock Detect signal. This Active High TTL output is a
clock recovery indicator. It is set high when the inter-
nal clock recovery circuitry has locked onto the in-
coming data stream.
DIP SWITCH
An on-board DIP switch provides control capability.
The switch functions are described in the following
sections.
SEL[1:0]. Mode select. TTL. These two switches are
used to select the input (reference clock) frequen-
cies, as shown in Table 2.
SEL1
SEL0
INPUT FREQ
0
0
51.84 MHz
1
0
19.44 MHz
0
1
19.44 MHz
1
1
155.32 MHz
Table 2. SEL[1:0] Switch Function
S3014 EVALUATION BOARD
S6003
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 3
May 17, 1994
SEL2
OUTPUT FREQ
0
622.08 MHz
1
155.52 MHz
Table 3. SEL2 Switch Function
RST. Reset. TTL. Active Low. Initializes the S3014 to
a known state and forces the PLL to acquire to the
reference clock.
TSTCLKEN. Test Clock Enable. TTL. Active High.
Used to bypass the VCO in the PLL.
LOS. Loss of Signal. ECL. When this switch is set
Low (0), the S3014 is locked to the reference clock.
When it is set High (1), the S3014 is locked to data
and data is processed normally.
SEL2. Mode Select. TTL. This switch sets the output
frequencies, as shown in Table 3.
SERDATIP
SERDATIN
JP1
JP2
JP3
SERDATIP
SERDATIN
JP1
JP2
JP3
DIFFERENTIAL
INPUTS
SINGLE-ENDED
INPUT
JUMPER CONFIGURATION
The jumpers labeled JP4 in Figure 1 allow the user to
control whether an onboard crystal reference or ex-
ternal clock reference is used (see Crystal References,
Fig. 2).
In addition, the jumpers labeled JP1, JP2, and JP3 in
Figure 1 must be properly configured for differential or
single-ended data inputs. When providing single-ended
data into the SERDATIP SMA connector, an on-board
single-ended to differential converter provides clean full
swing ECL levels to the S3014 device. Jumper configu-
ration options are shown in Figure 3.
S3014 EVALUATION BOARD
S6003
Figure 3. Jumper Configurations for Inputs
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