July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Am29LV160M
Data Sheet
Publication Number 25974 Revision B Amendment 0 Issue Date August 11, 2003
Publication Number 25974 Revision B Amendment 0 Issue Date August 11, 2003
PRELIMINARY
Am29LV160M
16 Megabit (2 M x 8-Bit/1 M x 16-Bit) MirrorBit
TM
3.0 Volt-only Boot Sector Flash Memory
Data Sheet
Distinctive Characteristics
Architectural Advantages
Single power supply operation
-- 3 V for read, erase, and program operations
Manufactured on 0.23 m MirrorBit
TM
process
technology
-- Fully compatible with Am29LV160D device
SecSi
TM
(Secured Silicon) Sector region
-- 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
-- May be programmed and locked at the factory or by
the customer
Flexible sector architecture
-- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-
one 64 Kbyte sectors (byte mode)
-- One 8 Kword, two 4 Kword, one 16 Kword, and thirty-
one 32 Kword sectors (word mode)
Compatibility with JEDEC standards
-- Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
Top or bottom boot block configurations available
Minimum 100,000 erase cycle guarantee per sector
20-year data retention at 125C
Performance Characteristics
High performance
-- Access times as fast as 70 ns
-- 0.7 s typical sector erase time
Low power consumption (typical values at 5 MHz)
-- 400 nA standby mode current
-- 15 mA read current
-- 40 mA program/erase current
-- 400 nA Automatic Sleep mode current
Package options
-- 48-ball Fine-pitch BGA
-- 64-ball Fortified BGA
-- 48-pin TSOP
Software Features
-- Program Suspend & Resume: read other sectors
before programming operation is completed
-- Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
-- Data# polling & toggle bits provide status
-- Unlock Bypass Program command reduces overall
multiple-word programming time
-- CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Hardware Features
-- Sector Protection: hardware-level method of
preventing write operations within a sector
-- Temporary Sector Unprotect: V
ID
-level method of
changing code in locked sectors
-- Hardware reset input (RESET#) resets device
-- Ready/Busy# output (RY/BY#) indicates program or
erase cycle completion
2
Am29LV160M
25974B0 August 11, 2003
P r e l i m i n a r y
General Description
The Am29LV160M is a 16 Mbit, 3.0 Volt-only Flash memory organized as
2,097,152 bytes or 1,048,576 words. The device is offered in a 48-ball Fine-pitch
BGA, 64-ball Fortified BGA, and 48-pin TSOP packages. The word-wide data (x16)
appears on DQ15DQ0; the byte-wide (x8) data appears on DQ7DQ0. The de-
vice requires only a single 3.0 volt power supply for both read and write
functions, designed to be programmed in-system with the standard system 3.0
vo lt V
C C
sup pl y. The de vic e c an a lso be p rog ra m m e d i n sta nd a rd
EPROM programmers.
The device offers access times of 70, 85, 90, and 100 ns. To eliminate bus conten-
tion the device has separate chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
The device is entirely command set compatible with the JEDEC single-power-
supply Flash standard. Commands are written to the device using standard
microprocessor write timing. Write cycles also internally latch addresses and data
needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll
the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/
Busy# (RY/BY#) output to determine whether the operation is complete. To
facilitate programming, an Unlock Bypass mode reduces command sequence
overhead by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low V
CC
detector that automati-
cally inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The Program Suspend/Program Resume fea-
ture enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would thus also reset the de-
vice, enabling the host system to read boot-up firmware from the Flash memory
device.
The device reduces power consumption in the standby mode when it detects
specific voltage levels on CE# and RESET#, or when addresses have been stable
for a specified period of time.
The SecSiTM (Secured Silicon) Sector provides a 128-word/256-byte area for
code or data that can be permanently protected. Once this sector is protected, no
further changes within the sector can occur.
MirrorBit flash technology combines years of Flash memory manufacturing expe-
rience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via hot-hole
assisted erase. The data is programmed using hot electron injection.
August 11, 2003 25974B0
Am29LV160M
3
P r e l i m i n a r y
Table of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29LV160M Device Bus Operations .......................10
Word/Byte Configuration .................................................................. 10
Requirements for Reading Array Data ........................................... 10
Writing Commands/Command Sequences .....................................11
Program and Erase Operation Status ...............................................11
Standby Mode ...........................................................................................11
Automatic Sleep Mode .........................................................................12
RESET#: Hardware Reset Pin .............................................................12
Output Disable Mode ...........................................................................12
Table 2. Sector Address Tables (Am29LV160MT) ...................13
Table 3. Sector Address Tables (Am29LV160MB) ...................14
Autoselect Mode ....................................................................................15
Table 4. Autoselect Codes (High Voltage Method) ..................15
Sector Protection/Unprotection .......................................................15
Temporary Sector Unprotect ............................................................16
Figure 1. Temporary Sector Unprotect Operation................... 16
Figure 2. In-System Single High Voltage Sector Protect/
Unprotect Algorithms ........................................................ 17
SecSi (Secured Silicon) Sector Flash Memory Region ................ 18
Table 5. SecSi Sector Addressing ........................................18
Customer Lockable: SecSi Sector NOT Programmed or Protect-
ed At the Factory .................................................................................. 18
Figure 3. SecSi Sector Protect Verify ................................... 19
Common Flash Memory Interface (CFI) ....................................... 20
Table 6. CFI Query Identification String ...............................20
Table 7. System Interface String .........................................21
Table 8. Device Geometry Definition ....................................21
Table 9. Primary Vendor-Specific Extended Query .................22
Hardware Data Protection ................................................................22
Low V
CC
Write Inhibit ........................................................................22
Write Pulse "Glitch" Protection ......................................................22
Logical Inhibit ..........................................................................................23
Power-Up Write Inhibit ......................................................................23
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data ..............................................................................23
Reset Command ....................................................................................23
Autoselect Command Sequence ......................................................24
Word/Byte Program Command Sequence ...................................24
Unlock Bypass Command Sequence ...............................................25
Figure 4. Program Operation .............................................. 25
Chip Erase Command Sequence ......................................................26
Sector Erase Command Sequence ...................................................26
Erase Suspend/Erase Resume Commands .....................................27
Figure 5. Erase Operation .................................................. 28
Program Suspend/Program Resume Command Sequence ...... 28
Figure 6. Program Suspend/Program Resume ....................... 29
Command Definitions Tables ............................................................30
Write Operation Status . . . . . . . . . . . . . . . . . . . . .32
DQ7: Data# Polling ..............................................................................32
Figure 7. Data# Polling Algorithm....................................... 33
RY/BY#: Ready/Busy# .......................................................................... 33
DQ6: Toggle Bit I ..................................................................................34
DQ2: Toggle Bit II .................................................................................34
Reading Toggle Bits DQ6/DQ2 ........................................................35
Figure 8. Toggle Bit Algorithm............................................ 36
DQ5: Exceeded Timing Limits ..........................................................36
DQ3: Sector Erase Timer ...................................................................37
Table 12. Write Operation Status ........................................ 37
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .38
Figure 9. Maximum Negative Overshoot Waveform ............... 38
Figure 10. Maximum Positive Overshoot Waveform ............... 38
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 38
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .39
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Test Setup........................................................ 40
Table 13. Test Specifications .............................................. 40
Figure 12. Input Waveforms and Measurement Levels ........... 40
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 41
Read Operations ....................................................................................41
Figure 13. Read Operations Timings.................................... 41
Hardware Reset (RESET#) .................................................................42
Figure 14. RESET# Timings ............................................... 42
Word/Byte Configuration (BYTE#) ..............................................43
Figure 15. BYTE# Timings for Read Operations..................... 43
Figure 16. BYTE# Timings for Write Operations .................... 43
Erase/Program Operations ................................................................44
Figure 17. Program Operation Timings ................................ 45
Figure 18. Chip/Sector Erase Operation Timings ................... 46
Figure 19. Data# Polling Timings
(During Embedded Algorithms) .......................................... 47
Figure 20. Toggle Bit Timings
(During Embedded Algorithms) .......................................... 47
Figure 21. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations ................................................. 48
Figure 22. Temporary Sector Unprotect/Timing Diagram........ 48
Figure 23. Sector Protect/Unprotect Timing Diagram ............. 49
Figure 24. Alternate CE# Controlled Write Operation Timings . 51
Erase and Programming Performance . . . . . . . . .52
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 52
TSOP Pin and BGA Package Capacitance . . . . . 52
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .53
TS 048--48-Pin Standard TSOP ......................................................53
TSR048--48-Pin Reverse TSOP ......................................................54
FBA048--48-Ball Fine-Pitch Ball Grid Array (BGA)
6 x 8 mm Package .................................................................................55
LAA064--64-Ball Fortified Ball Grid Array (BGA)
13 x 11 mm Package ................................................................................56
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . .57
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