ChipFind - документация

Электронный компонент: 85C30

Скачать:  PDF   ZIP





Publication# 10216
Rev. F
Amendment /0
Issue Date: June 1993
Advanced
Micro
Devices
Am85C30
Enhanced Serial Communications Controller
FINAL
DISTINCTIVE CHARACTERISTICS
s
Fastest data rate of any Am8530
-- 8.192 MHz / 2.048 Mb/s
-- 10 MHz / 2.5 Mb/s
-- 16.384 MHz / 4.096 Mb/s
s
Low-power CMOS technology
s
Pin and function compatible with other NMOS
and
CMOS 8530s
s
Easily interfaced with most CPUs
-- Compatible with non-multiplexed bus
s
Many enhancements over NMOS Am8530H
-- Allows Am85C30 to be used more effectively in
high-speed applications
-- Improves interface capabilities
s
Two independent full-duplex serial channels
s
Asynchronous mode features
-- Programmable stop bits, clock factor, character
length and parity
-- Break detection/generation
-- Error detection for framing, overrun, and parity
s
Synchronous mode features
-- Supports IBM
BISYNC, SDLC, SDLC Loop,
HDLC, and ADCCP Protocols
-- Programmable CRC generators and checkers
-- SDLC/HDLC support includes frame control,
zero insertion and deletion, abort, and residue
handling
s
Enhanced SCC functions support high-speed
frame reception using DMA
-- 14-bit byte counter
-- 10
19 SDLC/HDLC Frame Status FIFO
-- Independent Control on both channels
-- Enhanced operation does not allow special
receive conditions to lock the 3-byte DATA
FIFO when the 10
19 FIFO is enabled
s
Local Loopback and Auto Echo modes
s
Internal or external character synchronization
s
2-Mb/s FM encoding transmit and receive
capability using internal DPLL for 16.384-MHz
product
s
Internal synchronization between RxC to PCLK
and TxC to PCLK
-- This allows the user to eliminate external syn-
chronization hardware required by the NMOS
device when transmitting or receiving data at
the maximum rate of 1/4 PCLK frequency
GENERAL DESCRIPTION
AMD's Am85C30 is an enhanced pin-compatible ver-
sion of the popular Am8530H Serial Communications
Controller. The Enhanced Serial Communications
Controller (ESCC) is a high-speed, low-power, multi-
protocol communications peripheral designed for use
with 8- and 16-bit microprocessors. It has two independ-
ent,full-duplex channels and functions as a serial-to-
parallel, parallel-to-serial converter/controller. AMD's
proprietary enhancements make the Am85C30 easier
to interface and more effective in high-speed applica-
tions due to a reduction in software burden and the elimi-
nation of the need for some external glue logic.
The Am85C30 is easy to use due to a variety of sophisti-
cated internal functions, including on-chip baud rate
generators, digital phase-locked loops, and crystal
oscillators, which dramatically reduce the need for ex-
ternal logic. The device can generate and check CRC
codes in any SYNC mode, and can be programmed to
check data integrity in various modes. The ESCC also
has facilities for modem controls in both channels. In ap-
plications where these controls are not needed, the mo-
dem controls can be used for general-purpose I/O.
This versatile device supports virtually any serial data
transfer application such as networks, modems, cas-
settes, and tape drivers. The ESCC is designed for non-
multiplexed buses and is easily interfaced with most
CPUs, such as 80188, 80186, 80286, 8080, Z80, 6800,
68000 and MULTIBUS
TM
.
AMD
2
Am85C30
Enhancements that allow the Am85C30 to be used
more effectively in high-speed applications include:
s
A 10
19 bit SDLC/HDLC frame status FIFO array
s
A 14-bit SDLC/HDLC frame byte counter
s
Automatic SDLC/HDLC opening frame flag
transmission
s
TxD pin forced High in SDLC NRZI mode after
closing flag
s
Automatic SDLC/HDLC Tx underrun/EOM flag
reset
s
Automatic SDLC/HDLC Tx CRC generator reset/
preset
s
RTS
synchronization to closing SDLC/HDLC flag
DTR
/
REQ
deactivation delay significantly reduced
s
External PCLK to
RxC
or
TxC
synchronization
requirement eliminated for PCLK divide-by-four
operation
Other enhancements to improve the Am85C30 inter-
face capabilities include:
s
Write data valid setup time to falling edge of
WR
requirement eliminated
s
Reduced
INT
response time
s
Reduced access recovery time (t
RC
) to 3 PCLK
best case (3 1/2 PCLK worst case)
s
Improved
Wait
timing
s
Write Registers WR3, WR4, WR5, and WR10
made readable
s
Lower priority interrupt masking without
INTACK
s
Complete SDLC/HDLC CRC character reception
BLOCK DIAGRAM
Data
Control
CPU
Bus VO
Internal
Control
Logic
Internal Bus
Channel
A
Registers
Interrupt
Control
Logic
Channel
B
Registers
+5 V GND PCLK
Channel A
Channel B
Control
Logic
Transmitter
Receiver
Baud
Rate
Generator
10
19 Bit
Frame
Status
FIFO
Interrupt
Control Lines
5
10216F-1
8
TxDA
RxDA
RTxCA
TRxCA
DTR/REQA
SYNCA
W/REQA
RTSA
CTSA
DCDA
TxDB
RxDB
RTxCB
TRxCB
DTR/REQB
SYNCB
W/REQB
RTSB
CTSB
DCDB
RELATED AMD PRODUCTS
Part No.
Description
Part No.
Description
Am7960
Coded Data Transceiver
Am9517A
DMA Controller
80186
Highly Integrated 16-Bit
5380, 53C80
SCSI Bus Controller
Microprocessor
80188
Highly Integrated 8-Bit
80286, 80C286
High-Performance 16-Bit
Microprocessor
Microprocessor
Am386
High-Performance 32-Bit
Microprocessor
AMD
3
Am85C30
CONNECTION DIAGRAMS
Top View
D
0
D
2
D
4
D
6
RD
WR
A/
B
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Am85C30
10216F-2
10216F-3
Note:
Pin 1 is marked for orientation.
DIP
D
1
D
3
D
5
D
7
INT
IEO
IEI
INTACK
+5 V
W/REQA
SYNCA
RTxCA
RxDA
TRxCA
TxDA
DTR/REQA
RTSA
CTSA
DCDA
PCLK
CE
D/
C
GND
W/REQB
SYNCB
RTxCB
RxDB
TRxCB
TxDB
DTR/REQB
RTSB
CTSB
DCDB
1 44 43 42
5
4
3
2
6
41 40
7
8
9
10
11
12
13
14
15
16
17
23 24 25 26
19 20 21 22
18
27 28
39
38
37
36
35
34
33
32
31
30
29
IEO
IEI
INTACK
+5 V
W
/
REQA
SYNCA
RTxCA
RxDA
TRxCA
TxDA
NC
A/
B
CE
D/
C
NC
GND
W
/
REQB
SYNCB
RTxCB
RxDB
TRxCB
TxDB
INT
D
7
D
5
D
3
D
1
D
0
D
2
D
4
D
6
RD
WR
NC
DTR
/
REQA
RTSA
CTSA
DCDA
PCLK
DCDB
CTSB
RTSB
DTR
/
REQB
NC
PLCC, LCC
LOGIC SYMBOL
D
7
D
0
RD
WR
A/
B
CE
D/
C
TxDA
RxDA
TRxCA
RTxCA
SYNCA
W
/
REQA
DTR
/
REQA
RTSA
CTSA
DCDA
TxDB
RxDB
TRxCB
RTxCB
Serial
Data
Channel
Clocks
Channel
Controls
for
Modem,
DMA, or
Other
Serial
Data
Channel
Clocks
Data
Bus
Control
+5 V GND
PCLK
8
Channel
Controls
for
Modem,
DMA, or
Other
Bus Timing
and Reset
Interrupt
10216F-4
SYNCB
W/REQB
DTR/REQB
RTSB
CTSB
DCDB
INT
INTACK
IEI
IE0
AMD
4
Am85C30
ORDERING INFORMATION
Commodity Products
-8 = 8.192 MHz
-10 = 10 MHz
-16 = 16.384 MHz
AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
AM85C30
P
C
OPTIONAL PROCESSING
TEMPERATURE RANGE
C = Commercial (0 to +70
C)
PACKAGE TYPE
P = 40-Pin Plastic DIP (PD 040)
J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
SPEED OPTION
DEVICE NUMBER/DESCRIPTION
Am85C30
Enhanced Serial Communications Controller
Blank = Standard Processing
Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and check on newly
released combinations.
Valid Combinations
AM85C30-8
AM85C30-10
AM85C30-16
PC, JC
-10
AMD
5
Am85C30
ORDERING INFORMATION
Industrial Products
AMD industrial products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
AM85C30
J
I
I = Industrial (-40 to +85
C)
J = 44-Pin Leadless Chip Carrier (PL 044)
-10 = 10 MHz
-16 = 16.384 MHz
Am85C30
Enhanced Serial Communications Controller
Blank = Standard Processing
Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and check on newly
released combinations.
Valid Combinations
AM85C30-10
AM85C30-16
JI
-10
OPTIONAL PROCESSING
TEMPERATURE RANGE
PACKAGE TYPE
SPEED OPTION
DEVICE NUMBER/DESCRIPTION