This Data Sheet states AMD's current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 21522

Rev: D Amendment/+1

Issue Date: November 13, 2000

Am29LV004B

4 Megabit (512 K x 8-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

Single power supply operation

-- 2.7 to 3.6 volt read and write operations for

battery-powered applications

Manufactured on 0.32 µm process technology

-- Compatible with 0.5 µm Am29LV004 device

High performance

-- Access times as fast as 70 ns

Ultra low power consumption (typical values at
5 MHz)

-- 200 nA Automatic Sleep mode current

-- 200 nA standby mode current

-- 7 mA read current

-- 15 mA program/erase current

Flexible sector architecture

-- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seven 64 Kbyte sectors

-- Supports full chip erase

-- Sector Protection features:

A hardware method of locking a sector to
prevent any program or erase operations within
that sector

Sectors can be locked in-system or via
programming equipment

Temporary Sector Unprotect feature allows code
changes in previously locked sectors

Unlock Bypass Program Command

-- Reduces overall programming time when

issuing multiple program command sequences

Top or bottom boot block configurations
available

Embedded Algorithms

-- Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

-- Embedded Program algorithm automatically

writes and verifies data at specified addresses

Minimum 1,000,000 write cycle guarantee per sector

20-year data retention at 125

-- Reliable operation for the life of the system

Package option

-- 40-pin TSOP

Compatibility with JEDEC standards

-- Pinout and software compatible with single-

power supply Flash

-- Superior inadvertent write protection

Data# Polling and toggle bits

-- Provides a software method of detecting

program or erase operation completion

Ready/Busy# pin (RY/BY#)

-- Provides a hardware method of detecting

program or erase cycle completion

Erase Suspend/Erase Resume

-- Suspends an erase operation to read data from,

or program data to, a sector that is not being
erased, then resumes the erase operation

Hardware reset pin (RESET#)

-- Hardware method to reset the device to reading

array data

Am29LV004B

GENERAL DESCRIPTION

The Am29LV004B is an 4 Mbit, 3.0 volt-only Flash
memory organized as 524,288 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)
data appears on DQ7DQ0. This device requires only
a single, 3.0 volt VCC supply to perform read, program,
and erase operations. A standard EPROM programmer
can also be used to program and erase the device.

This device is manufactured using AMD's 0.32 µm
process technology, and offers all the features and ben-
efits of the Am29LV004, which was manufactured using
0 . 5 µ m p r o c e s s t e c h n o l o g y. I n a d d i t i o n , t h e
Am29LV004B features unlock bypass programming
and in-system sector protection/unprotection.

The standard device offers access times of 70, 90, and
120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm--an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.

Device erasure o ccu rs by executin g th e era se
command sequence. This initiates the Embedded Erase
algorithm--an internal algorithm that automatically
pre-programs the array (if it is not already programmed)

before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.

The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low
V

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.

AMD's Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.

Am29LV004B

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Am29LV004B Device Bus Operations ................................ 8

Requirements for Reading Array Data ..................................... 8
Writing Commands/Command Sequences .............................. 8
Program and Erase Operation Status ...................................... 9
Standby Mode .......................................................................... 9
Automatic Sleep Mode ............................................................. 9
RESET#: Hardware Reset Pin ................................................. 9
Output Disable Mode ................................................................ 9

Table 2. Am29LV004BT Top Boot Block Sector Address Table..... 10
Table 3. Am29LV004BB Bottom Boot Block Sector Address Table 10

Autoselect Mode ..................................................................... 11

Table 4. Am29LV004B Autoselect Codes (High Voltage Method).. 11

Sector Protection/Unprotection ............................................... 11
Temporary Sector Unprotect .................................................. 11

Figure 1. In-System Sector Protect/Unprotect Algorithms ...............12
Figure 2. Temporary Sector Unprotect Operation ...........................13

Hardware Data Protection ...................................................... 13
Low V

Write Inhibit .............................................................. 13

Write Pulse "Glitch" Protection ............................................... 13
Logical Inhibit .......................................................................... 13
Power-Up Write Inhibit ............................................................ 13

Command Definitions . . . . . . . . . . . . . . . . . . . . . 13

Reading Array Data ................................................................ 13
Reset Command ..................................................................... 14
Autoselect Command Sequence ............................................ 14
Byte Program Command Sequence ....................................... 14
Unlock Bypass Command Sequence ..................................... 14

Figure 3. Program Operation ..........................................................15

Chip Erase Command Sequence ........................................... 15
Sector Erase Command Sequence ........................................ 15
Erase Suspend/Erase Resume Commands ........................... 16

Figure 4. Erase Operation ...............................................................16

Command Definitions ............................................................. 17

Table 5. Am29LV004B Command Definitions................................. 17

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 18

DQ7: Data# Polling ................................................................. 18

Figure 5. Data# Polling Algorithm ...................................................18

RY/BY#: Ready/Busy# ........................................................... 19
DQ6: Toggle Bit I .................................................................... 19
DQ2: Toggle Bit II ................................................................... 19

Reading Toggle Bits DQ6/DQ2 ............................................... 19
DQ5: Exceeded Timing Limits ................................................ 20
DQ3: Sector Erase Timer ....................................................... 20

Figure 6. Toggle Bit Algorithm ........................................................ 20
Table 6. Write Operation Status..................................................... 21

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 22

Figure 7. Maximum Negative Overshoot Waveform ...................... 22
Figure 8. Maximum Positive Overshoot Waveform ........................ 22

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. I

CC1

Current vs. Time (Showing Active and Automatic

Sleep Currents) .............................................................................. 24
Figure 10. Typical I

CC1

vs. Frequency ........................................... 24

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11. Test Setup ..................................................................... 25
Table 7. Test Specifications ........................................................... 25

Key to Switching Waveforms. . . . . . . . . . . . . . . . 25

Figure 12. Input Waveforms and Measurement Levels ................. 25

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

Read Operations .................................................................... 26

Figure 13. Read Operations Timings ............................................. 26

Hardware Reset (RESET#) .................................................... 27

Figure 14. RESET# Timings .......................................................... 27

Erase/Program Operations ..................................................... 28

Figure 15. Program Operation Timings .......................................... 29
Figure 16. Chip/Sector Erase Operation Timings .......................... 30
Figure 17. Data# Polling Timings (During Embedded Algorithms) . 31
Figure 18. Toggle Bit Timings (During Embedded Algorithms) ...... 31
Figure 19. DQ2 vs. DQ6 ................................................................. 32

Temporary Sector Unprotect .................................................. 32

Figure 20. Temporary Sector Unprotect Timing Diagram .............. 32
Figure 21. Sector Protect/Unprotect Timing Diagram .................... 33

Alternate CE# Controlled Erase/Program Operations ............ 34

Figure 22. Alternate CE# Controlled Write Operation Timings ...... 35

Erase and Programming Performance . . . . . . . 36
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 36
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 36
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 37

TS 040--40-Pin Standard TSOP ............................................ 37
TSR040--40-Pin Reverse TSOP ........................................... 38

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 39

Revision A (January 1998) ..................................................... 39
Revision B (June 1998) .......................................................... 39
Revision C (January 1999) ..................................................... 39
Revision D (November 18, 1999) ........................................... 39
Revision D+1 (November 13, 2000) ....................................... 39

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AAM29LV004BB-120EC

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AAM29LV004BB-120EC