FINAL
Publication# 12082
Rev: F Amendment/0
Issue Date: May 1998
Am27X256
256 Kilobit (32 K x 8-Bit) CMOS ExpressROM Device
DISTINCTIVE CHARACTERISTICS
s
As an OTP EPROM alternative:
-- Factory optimized programming
-- Fully tested and guaranteed
s
As a Mask ROM alternative:
-- Shorter leadtime
-- Lower volume per code
s
Fast access time
-- 55 ns
s
Single +5 V power supply
s
Compatible with JEDEC-approved EPROM
pinout
s
10% power supply tolerance
s
High noise immunity
s
Low power dissipation
-- 20 A maximum CMOS standby current
s
Available in Plastic Dual-In-line Package (PDIP)
and Plastic Leaded Chip Carrier (PLCC)
s
Latch-up protected to 100 mA from 1 V to
V
CC
+ 1 V
s
Versatile features for simple interfacing
-- Both CMOS and TTL input/output compatibility
-- Two line control functions
GENERAL DESCRIPTION
The Am27X256 is a factory programmed and tested
OTP EPROM. It is programmed after packaging prior to
final test. Every device is rigorously tested under AC
and DC operating conditions to your stable code. It is
organized as 32 Kwords by 8 bits per word and is avail-
able in plastic dual in-line packages (PDIP), as well as
plastic leaded chip carrier (PLCC) packages. Express-
ROM devices provide a board-ready memory solution
for medium to high volume codes with short leadtimes.
This offers manufacturers a cost-effective and flexible
alternative to OTP EPROMs and mask programmed
ROMs.
Data can be accessed as fast as 55 ns, allowing
high-performance microprocessors to operate with re-
duced WAIT states. The device offers separate Output
Enable (OE#) and Chip Enable (CE#) controls, thus
eliminating bus contention in a multiple bus micropro-
cessor system.
AMD's CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 80 mW in active mode, and
100 W in standby mode.
BLOCK DIAGRAM
12082F-1
A0A14
Address
Inputs
CE#
OE#
V
CC
V
SS
Data Outputs DQ0DQ7
Output
Buffers
Y
Gating
262,144
Bit Cell
Matrix
X
Decoder
Y
Decoder
Output Enable
Chip Enable
and
Prog Logic
2
Am27X256
PRODUCT SELECTOR GUIDE
CONNECTION DIAGRAMS
Top View
DIP
PLCC
Notes:
1. JEDEC nomenclature is in parenthesis.
2. Don't use (DU) for PLCC.
PIN DESIGNATIONS
A0A14
= Address Inputs
CE# (E#)
= Chip Enable Input
DQ0DQ7
= Data Input/Outputs
OE# (G#)
= Output Enable Input
PGM# (P#)
= Program Enable Input
V
CC
= V
CC
Supply Voltage
V
PP
= Program Voltage Input
V
SS
= Ground
NC
= No Internal Connection
LOGIC SYMBOL
Family Part Number
Am27X256
Speed Options
V
CC
= 5.0 V
5%
-255
V
CC
= 5.0 V
10%
-55
-70
-90
-120
-150
-200
Max Access Time (ns)
55
70
90
120
150
200
250
CE# (E#) Access (ns)
55
70
90
120
150
200
250
OE# (G#) Access (ns)
35
40
40
50
50
50
50
3
4
5
2
1
9
10
11
12
13
23
22
21
20
19
7
8
18
17
6
28
27
16
14
26
25
24
15
A6
A5
A4
A3
A2
A1
A0
DQ0
A7
DQ1
DQ2
V
SS
A8
A9
A11
OE# (G#)
A10
CE# (E#)
DQ7
V
CC
A14
DQ6
A13
DQ5
DQ4
DQ3
V
PP
A12
12082F-2
DQ5
DU
DQ4
DQ3
DU
1
31 30
2
3
4
5
6
7
8
9
10
11
12
13
17 18 19 20
16
15
14
29
28
27
26
25
24
23
22
21
32
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
A8
A9
A11
NC
OE# (G#)
A10
CE# (E#)
DQ7
DQ6
A7
A12
V
PP
V
CC
A14
A13
DQ1
DQ2
V
SS
12082F-3
15
8
DQ0DQ7
A0A14
CE# (E#)
OE# (G#)
12082F-4
Am27X256
3
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am27X256
256 Kilobit (32 K x 8-Bit) CMOS ExpressROM Device
AM27X256
-55
J
C
CODE DESIGNATION
Assigned by AMD
TEMPERATURE RANGE
C = Commercial (0
C to +70
C)
I
= Industrial (40
C to +85
C)
PACKAGE TYPE
P
= 28-Pin Plastic Dual In-Line Package (PD 028)
J
= 32-Pin Plastic Leaded Chip Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
XXXXX
Valid Combinations
AM27X256-55
PC, JC
AM27X256-70
PC, JC, PI, JI
AM27X256-90
AM27X256-120
AM27X256-150
AM27X256-200
AM27X256-255
V
CC
= 5.0 V
5%
4
Am27X256
FUNCTIONAL DESCRIPTION
Read Mode
To obtain data at the device outputs, Chip Enable (CE#)
and Output Enable (OE#) must be driven low. CE# con-
trols the power to the device and is typically used to se-
lect the device. OE# enables the device to output data,
independent of device selection. Addresses must be
stable for at least t
ACC
t
OE
.
Refer to the Switching
Waveforms section for the timing diagram.
Standby Mode
The device enters the CMOS standby mode when CE#
is at V
CC
0.3 V. Maximum V
CC
current is reduced to
100 A. The device enters the TTL-standby mode
when CE# is at V
IH
. Maximum V
CC
current is reduced
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, indepen-
dent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function provides:
s
Low memory power dissipation, and
s
Assurance that output bus contention will not occur.
CE# should be decoded and used as the primary de-
vice-selecting function, while OE# be made a common
connection to all devices in the array and connected to
the READ line from the system control bus. This as-
sures that all deselected memory devices are in their
low-power standby mode and that the output pins are
only active when data is desired from a particular mem-
ory device.
System Applications
During the switch between active and standby condi-
tions, transient current peaks are produced on the ris-
ing and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1 F ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
V
CC
and V
SS
to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on Express-
ROM device arrays, a 4.7 F bulk electrolytic capacitor
should be used between V
CC
and V
SS
for each eight
devices. The location of the capacitor should be close
to where the power supply is connected to the array.
MODE SELECT TABLE
Note:
X = Either V
IH
or V
IL
.
Mode
CE#
OE#
V
PP
Outputs
Read
V
IL
V
IL
X
D
OUT
Output Disable
X
V
IH
X
High Z
Standby (TTL)
V
IH
X
X
High Z
Standby (CMOS)
V
CC
0.3 V
X
X
High Z
Am27X256
5
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
OTP Products. . . . . . . . . . . . . . . . . . 65
C to +125
C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . 55
C to +125
C
Voltage with Respect to V
SS
All pins except V
CC
. . . . . . . . . 0.6 V to V
CC
+ 0.6 V
V
CC
(Note 1). . . . . . . . . . . . . . . . . . . . . 0.6 V to 7.0 V
Note:
1. Minimum DC voltage on input or I/O pins 0.5 V. During
voltage transitions, the input may overshoot V
SS
to 2.0 V
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is V
CC
+ 5 V. During voltage transitions, input
and I/O pins may overshoot to V
CC
+ 2.0 V for periods up
to 20ns.
Stresses above those listed under "Absolute Maximum Rat-
ings" may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for extended periods
may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T
A
) . . . . . . . . . . .0
C to +70
C
Industrial (I) Devices
Ambient Temperature (T
A
) . . . . . . . . .40
C to +85
C
Supply Read Voltages
V
CC
for 5% devices . . . . . . . . . . +4.75 V to +5.25 V
V
CC
for 10% devices . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
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