FINAL

Publication# 18880

Rev: C Amendment/+2

Issue Date: April 1998

Am28F512A

512 Kilobit (64 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms

DISTINCTIVE CHARACTERISTICS

High performance

-- 70 ns maximum access time

CMOS low power consumption

-- 30 mA maximum active current

-- 100 µA maximum standby current

-- No data retention power consumption

Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts

-- 32-pin PDIP

-- 32-pin PLCC

-- 32-pin TSOP

100,000 write/erase cycles minimum

Write and erase voltage 12.0 V

Latch-up protected to 100 mA from -1 V
to V

+1 V

Embedded Erase Electrical Bulk Chip-Erase

-- Two seconds typical chip-erase including

pre-programming

Embedded

Program

-- 4 µs typical byte-program including time-out

-- One second typical chip program

Command register architecture for
microprocessor/microcontroller compatible
write interface

On-chip address and data latches

Advanced CMOS flash memory technology

-- Low cost single transistor memory cell

Embedded

algorithms for completely

self-timed write/erase operations

GENERAL DESCRIPTION

The Am28F512A is a 512 Kbit Flash memory orga-
nized as 64 Kbytes of 8 bits each. AMD's Flash memo-
ries offer the most cost-effective and reliable read/write
non- volatile random access memory. The Am28F512A
is packaged in 32-pin PDIP, PLCC, and TSOP versions.
It is designed to be reprogrammed and erased in-sys-
tem or in sta ndard EPROM programmers. Th e
Am28F512A is erased when shipped from the factory.

The standard Am28F512A offers access times as fast
as 70 ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the Am28F512A has separate chip enable (CE#)
and output enable (OE#) controls.

AMD's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F512A uses a command register to manage this
functionality, while maintaining a JEDEC Flash stan-
dard 32-pin pinout. The command register allows for
100% TTL level control inputs and fixed power supply
levels during erase and programming.

AMD's Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The AMD cell is designed to optimize the erase and

programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low inter-
n a l e l e c tr i c f i e l d s fo r e r a se a n d p r o gr a m m i n g
operations produces reliable cycling. The Am28F512A
uses a 12.0 V

5% V

high voltage input to perform

the erase

and programming functions.

The highest degree of latch-up protection is achieved
with AMD's proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from 1 V to V

+1 V.

Embedded Program

The Am28F512A is byte programmable using the Em-
bedded Programming algorithm. The Embedded Pro-
gramming algorithm does not require the system to
time-out or verify the data programmed. The typical
r o o m t e m p e r a t u r e p r o g r a m m i n g t i m e o f t h e
Am28F512A is one second.

Embedded Erase

The entire chip is bulk erased using the Embedded
Erase algorithm. The Embedded

Erase algorithm auto-

matically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are

Am28F512A

controlled internal to the device. Typical erasure at room
temperature is accomplished in two seconds, including
programming.

AMD's Am28F512A is entirely pin and software com-
patible with AMD Am28F020A, Am28F010A, and
Am28F256A Flash memories.

Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine
which controls the erase and programming circuitry.
During write cycles, the command register internally
latches address and data needed for the program-
ming and erase operations. For system design simpli-
fication, the Am28F512A is designed to support either
WE# or CE controlled writes. During a system write
cycle, addresses are latched on the falling edge of
WE# or CE# whichever occurs last. Data is latched on
the rising edge of WE# or CE# whichever occurs first.

To simplify the following discussion, the WE# pin is
used as the write cycle control pin throughout the rest
of this text. All setup and hold times are with respect
to the WE# signal.

AMD's Flash technology combines years of EPROM
and EEPROM experience to produce the highest lev-
els of quality, reliability, and cost effectiveness. The
Am28F512A electrically erases all bits simulta-
neously using Fowler-Nordheim tunneling. The bytes
are programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.

Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms

Am28F512A with

Embedded Algorithms

Am28F512 using AMD Flashrite

and Flasherase Algorithms

Embedded
Programming
Algorithm vs.
Flashrite
Programming
Algorithm

AMD's Embedded Programming algorithm
requires the user to only write a program
set-up command and a program command
(program data and address). The device
automatically times the programming
pulse width, verifies the programming, and
counts the number of sequences. A status
bit, Data

Polling, provides the user with

the programming operation status.

The Flashrite Programming algorithm requires the
user to write a program set-up command, a program
command, (program data and address), and a
program verify command, followed by a read and
compare operation. The user is required to time the
programming pulse width in order to issue the
program verify command. An integrated stop timer
prevents any possibility of overprogramming.

Upon completion of this sequence, the data is read
back from the device and compared by the user with
the data intended to be written; if there is not a
match, the sequence is repeated until there is a
match or the sequence has been repeated 25 times.

Embedded Erase
Algorithm vs.
Flasherase Erase
Algorithm

AMD's Embedded Erase algorithm
requires the user to only write an erase set-
up command and erase command. The
device automatically pre-programs and
verifies the entire array. The device then
automatically times the erase pulse width,
verifies the erase operation, and counts
the number of sequences. A status bit,
Data

Polling, provides the user with the

erase operation status.

The Flasherase Erase algorithm requires the device
to be completely programmed prior to executing an
erase command.

To invoke the erase operation, the user writes an
erase set-up command, an erase command, and an
erase verify command. The user is required to time
the erase pulse width in order to issue the erase
verify command. An integrated stop timer prevents
any possibility of overerasure.

Upon completion of this sequence, the data is read
back from the device and compared by the user with
erased data. If there is not a match, the sequence is
repeated until there is a match or the sequence has
been repeated 1,000 times.

Am28F512A

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:

Valid Combinations

Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION
Am28F512A
512 Kilobit (64 K x 8-Bit) 12.0 Volt CMOS Flash Memory with Embedded Algorithms

AM28F512A -70

OPTIONAL PROCESSING
Blank = Standard Processing
B

= Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (40°C to +85°C)
E = Extended (55°C to +125°C)

PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION
See Product Selector Guide and Valid Combinations

Valid Combinations

AM28F512A-70

PC, PI, PE,

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

AM28F512A-90

AM28F512A-120

AM28F512A-150

AM28F512A-200

Am28F512A

PIN DESCRIPTION

A0A15

ddress Inputs for memory locations. Internal latches

hold addresses during write cycles.

)

Chip Enable active low input activates the chip's con-
trol logic and input buffers. Chip Enable high will dese-
lect the device and operates the chip in stand-by mode.

DQ0DQ7

Data Inputs during memory write cycles. Internal
latches hold data during write cycles. Data Outputs
during memory read cycles.

No Connect-corresponding pin is not connected
internally to the die.

)

Output Enable active low input gates the outputs of the
device through the data buffers during memory read
cycles. Output Enable is high during command
sequencing and program/erase operations.

Power supply for device operation. (5.0 V

5% or 10%)

Program voltage input. V

must be at high voltage in

order to write to the command register. The command
register controls all functions required to alter the mem-
ory array contents. Memory contents cannot be altered
when V

+2 V.

Ground.

)

Write Enable active low input controls the write function
of the command register to the memory array. The tar-
get address is latched on the falling edge of the Write
Enable pulse and the appropriate data is latched on the
rising edge of the pulse. Write Enable high inhibits
writing to the device.

Am28F512A

BASIC PRINCIPLES

This section contains descriptions about the device
read, erase, and program operations, and write opera-
tion status of the Am29FxxxA, 12.0 volt family of Flash
devices. References to some tables or figures may be
given in generic form, such as "Command Definitions
table", rather than "Table 1". Refer to the corresponding
data sheet for the actual table or figure.

The Am28FxxxA family uses 100% TTL-level control
inputs to manage the command register. Erase and
reprogramming operations use a fixed 12.0 V

high voltage input.

Read Only Memory

Without high V

voltage, the device functions as a

read only memory and operates like a standard
EPROM. The control inputs still manage traditional
read, standby, output disable, and Auto select modes.

Command Register

The command register is enabled only when high volt-
age is applied to the V

pin. The erase and repro-

gramming operations are only accessed via the
register. In addition, two-cycle commands are required
for erase and reprogramming operations. The tradi-
tional read, standby, output disable, and Auto select
modes are available via the register.

The device's command register is written using standard
microprocessor write timings. The register controls an
internal state machine that manages all device opera-
tions. For system design simplification, the device is de-
signed to support either WE# or CE# controlled writes.
During a system write cycle, addresses are latched on
the falling edge of WE# or CE# whichever occurs last.
Data is latched on the rising edge of WE# or CE# which-
ever occur first. To simplify the following discussion, the
WE# pin is used as the write cycle control pin throughout
the rest of this text. All setup and hold times are with re-
spect to the WE# signal.

OVERVIEW OF ERASE/PROGRAM
OPERATIONS

Embedded

Erase Algorithm

AMD now makes erasure extremely simple and reli-
able. The Embedded Erase algorithm requires the user
to only write an erase setup command and erase com-
mand. The device will automatically pre-program and
verify the entire array. The device automatically times
the erase pulse width, provides the erase verify and
counts the number of sequences. A status bit, Data#
Polling, provides feedback to the user as to the status
of the erase operation.

Embedded Programming Algorithm

AMD now makes programming extremely simple and
reliable. The Embedded Programming algorithm re-
quires the user to only write a program setup command
and a program command. The device automatically
times the programming pulse width, provides the pro-
gram verify and counts the number of sequences. A
status bit, Data# Polling, provides feedback to the user
as to the status of the programming operation.

DATA PROTECTION

The device is designed to offer protection against acci-
dental erasure or programming caused by spurious
system level signals that may exist during power transi-
tions. The device powers up in its read only state. Also,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences.

The device also incorporates several features to pre-
vent inadvertent write cycles resulting from V

power-up and power-down transitions or system noise.

Low V

Write Inhibit

To avoid initiation of a write cycle during V

power-up

and power-down, the device locks out write cycles for
V

< V

LKO

(see DC characteristics section for volt-

ages). When V

< V

LKO

, the command register is dis-

abled, all internal program/erase circuits are disabled,
and the device resets to the read mode. The device ig-
nores all writes until V

> V

LKO

. The user must ensure

that the control pins are in the correct logic state when
V

> V

LKO

to prevent unintentional writes.

Write Pulse "Glitch" Protection

Noise pulses of less than 10 ns (typical) on OE#, CE#
or WE# will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE# = V

CE# =V

or WE# = V

. To initiate a write cycle CE#

and WE# must be a logical zero while OE# is a logical
one.

Power-Up Write Inhibit

Power-up of the device with WE# = CE# = V

and

OE# = V

will not accept commands on the rising

edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.

Am28F512A

FUNCTIONAL DESCRIPTION

Description Of User Modes

Table 1.

Am28F512A Device Bus Operations (Notes 7 and 8)

Legend:
X = Don't care, where Don't Care is either V

or V

levels. V

PPL

= V

+ 2 V. See DC Characteristics for voltage levels

of V

PPH

. 0 V < An < V

+ 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

Notes:
1. V

PPL

may be grounded, connected with a resistor to ground, or < V

+ 2.0 V. V

PPH

is the programming voltage specified for

the device. Refer to the DC characteristics. When V

= V

PPL

, memory contents can be read but not written or erased.

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3. 11.5 < V

< 13.0 V. Minimum V

rise time and fall time (between 0 and V

voltages) is 500 ns.

4. Read operation with V

= V

PPH

may access array data or the Auto select codes.

5. With V

at high voltage, the standby current is I

+ I

(standby).

6. Refer to Table 3 for valid D

during a write operation.

7. All inputs are Don't Care unless otherwise stated, where Don't Care is either V

or V

levels. In the Auto select mode all

addresses except A

and A

must be held at V

8. If V

1.0 Volt, the voltage difference between V

and V

should not exceed 10.0 volts. Also, the Am28F256 has a V

rise time and fall time specification of 500 ns minimum.

Operation

CE#
(E#)

OE#
(G#)

WE#
(W#)

(Note 1)

I/O

Read-Only

Read

PPL

OUT

Standby

PPL

HIGH Z

Output Disable

PPL

HIGH Z

Auto-select Manufacturer
Code (Note 2)

PPL

(Note 3)

CODE

(01h)

Auto-select Device
Code (Note 2)

PPL

(Note 3)

CODE

(AEh)

Read/Write

Read

PPH

OUT

(Note 4)

Standby (Note 5)

PPH

HIGH Z

Output Disable

PPH

HIGH Z

Write

PPH

(Note 6)

Am28F512A

READ-ONLY MODE

When V

is less than V

+ 2 V, the command register

is inactive. The device can either read array or autose-
lect data, or be standby mode.

Read

The device functions as a read only memory when V

< V

+ 2 V.

The device has two control functions. Both

must be satisfied in order to output data. CE# controls
power to the device. This pin should be used for spe-
cific device selection. OE# controls the device outputs
and should be used to gate data to the output pins if a
device is selected.

Address access time t

ACC

is equal to the delay from

stable addresses to valid output data. The chip enable
access time t

is the delay from stable addresses and

stable CE# to valid data at the output pins. The output
enable access time is the delay from the falling edge of
OE# to valid data at the output pins (assuming the ad-
dresses have been stable at least t

ACC

- t

Standby Mode

The device has two standby modes. The CMOS
standby mode (CE# input held at V

0.5 V), con-

sumes less than 100 µA of current. TTL standby mode
(CE# is held at V

) reduces the current requirements

to less than 1 mA. When in the standby mode the out-
puts are in a high impedance state, independent of the
OE# input.

If the device is deselected during erasure, program-
ming, or program/erase verification, the device will
draw active current until the operation is terminated.

Output Disable

Output from the device is disabled when OE# is at a
logic high level. When disabled, output pins are in a
high impedance state.

Auto Select

Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol-
dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the board.

The Auto select mode allows the reading out of a binary
code from the device that will identify its manufacturer and
type. This mode is intended for the purpose of automati-
cally matching the device to be programmed with its cor-
responding programming algorithm. This mode is
functional over the entire temperature range of the device.

Programming In A PROM Programmer

To activate this mode, the programming equipment
must force V

(11.5 V to 13.0 V) on address A9. Two

identifier bytes may then be sequenced from the device
outputs by toggling address A0 from V

to V

. All other

address lines must be held at V

, and V

must

less than or equal to V

+ 2.0 V while using this Auto

select mode. Byte 0 (A0 = V

) represents the manufac-

turer code and byte 1 (A0 = V

) the device identifier

code. For the device the two bytes are given in the table
2 of the device data sheet. All identifiers for manufac-
turer and device codes will exhibit odd parity with the
MSB (DQ7) defined as the parity bit.

Table 2.

Am28F512A Auto Select Code

Type

Code

(HEX)

Manufacturer Code

Device Code

Am28F512A

ERASE, PROGRAM, AND READ MODE

When V

is equal to 12.0 V ± 5%, the command reg-

ister is active. All functions are available. That is, the
device can program, erase, read array or autoselect
data, or be standby mode.

Write Operations

High voltage must be applied to the V

pin in order to

activate the command register. Data written to the reg-
ister serves as input to the internal state machine. The
output of the state machine determines the operational
function of the device.

The command register does not occupy an address-
able memory location. The register is a latch that stores
the command, along with the address and data infor-
mation needed to execute the command. The register
is written by bringing WE# and CE# to V

, while OE#

is at V

. Addresses are latched on the falling edge of

WE#, while data is latched on the rising edge of the
WE# pulse. Standard microprocessor write timings are
used.

The device requires the OE# pin to be V

for write op-

erations. This condition eliminates the possibility for
bus contention during programming operations. In
order to write, OE# must be V

, and CE# and WE#

must be V

. If any pin is not in the correct state a write

command will not be executed.

Refer to AC Write Characteristics and the Erase/Pro-
gramming Waveforms for specific timing parameters.

Command Definitions

The contents of the command register default to 00h
(Read Mode) in the absence of high voltage applied to
the V

pin. The device operates as a read only

memory. High voltage on the V

pin enables the

command register. Device operations are selected by
writing specific data codes into the command register.
Table 3 in the device data sheet defines these register
commands.

Read Command

Memory contents can be accessed via the read com-
mand when V

is high. To read from the device, write

00h into the command register. Standard microproces-
sor read cycles access data from the memory. The de-
vice will remain in the read mode until the command
register contents are altered.

The command register defaults to 00h (read mode)
upon V

power-up. The 00h (Read Mode) register de-

fault helps ensure that inadvertent alteration of the
memory contents does not occur during the V

power

transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing parameters.

Table 3.

Am28F512A Command Definitions

Notes:
1. Bus operations are defined in Table 1.

2. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE

pulse.

X = Don't care.

3. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data latched on the rising edge of WE

4. Please reference Reset Command section.

Command

First Bus Cycle

Second Bus Cycle

Operation

(Note 1)

Address

(Note 2)

Data

(Note 3)

Operation

(Note 1)

Address

(Note 2)

Data

(Note 3)

Read Memory (Note 4)

Write

00h/FFh

Read

Read Auto select

Write

80h or 90h

Read

00h/01h

01h/AEh

Embedded Erase Set-up/
Embedded Erase

Write

30h

Write

30h

Embedded Program Set-up/
Embedded Program

Write

10h or 50h

Write

Reset (Note 4)

Write

00h/FFh

Write

00h/FFh

Am28F512A

FLASH MEMORY PROGRAM/ERASE
OPERATIONS

Embedded Erase Algorithm

The automatic chip erase does not require the device
to be entirely pre-programmed prior to executing the
Embedded set-up erase command and Embedded
erase command. Upon executing the Embedded erase
command the device automatically will program and
verify the entire memory for an all zero data pattern.
The system is

not required to provide any controls or

timing during these operations.

When the device is automatically verified to contain an
all zero pattern, a self-timed chip erase and verify be-
gin. The erase and verify operation are complete when
the data on DQ7 is "1" (see Write Operation Status sec-
tion) at which time the device returns to Read mode.
The system is not required to provide any control or
timing during these operations.

When using the Embedded Erase algorithm, the erase
automatically terminates when adequate erase margin

has been achieved for the memory array (no erase ver-
ify command is required). The margin voltages are in-
ternally generated in the same manner as when the
standard erase verify command is used.

The Embedded Erase Set-Up command is a command
only operation that stages the device for automatic
electrical erasure of all bytes in the array. Embedded
Erase Setup is performed by writing 30h to the com-
mand register.

To commence automatic chip erase, the command 30h
must be written again to the command register. The au-
tomatic erase begins on the rising edge of the WE and
terminates when the data on DQ7 is "1" (see Write Op-
eration Status section) at which time the device returns
to Read mode.

Figure 1 and Table 4 illustrate the Embedded Erase al-
gorithm, a typical command string and bus operation.

Table 4.

Embedded Erase Algorithm

Note: See AC and DC Characteristics for values of V

parameters. The V

power supply can be hard-wired to the device or

switchable. When V

is switched, V

PPL

may be ground, no connect with a resistor tied to ground, or less than V

+ 2.0 V. Refer

to Functional Description.

Bus Operations

Command

Comments

Standby

Wait for V

Ramp to V

PPH

(see Note)

Write

Embedded Erase Setup Command

Data = 30h

Embedded Erase Command

Data = 30h

Read

Data

Polling to Verify Erasure

Standby

Compare Output to FFh

Read

Available for Read Operations

START

Apply V

PPH

Erasure Completed

Data# Poll from Device

Write Embedded Erase Command

Write Embedded Erase Setup Command

18880C-6

Figure 1.

Embedded Erase Algorithm

Am28F512A

Embedded Programming Algorithm

The Embedded Program Setup is a command only op-
eration that stages the device for automatic program-
ming. Embedded Program Setup is performed by
writing 10h or 50h to the command register.

Once the Embedded Setup Program operation is per-
formed, the next WE# pulse causes a transition to an
active programming operation. Addresses are latched
on the falling edge of CE# or WE# pulse, whichever
happens later. Data is latched on the rising edge of
WE# or CE#, whichever happens first. The rising edge

of WE# also begins the programming operation. The
system is not required to provide further controls or
timings. The device will automatically provide an ade-
quate internally generated program pulse and verify
margin. The automatic programming operation is
completed when the data on DQ7 is equivalent to data
written to this bit (see Write Operation Status section)
at which time the device returns to Read mode.

Figure 2 and Table 5 illustrate the Embedded Program
algorithm, a typical command string, and bus operation.

Table 5.

Embedded Programming Algorithm

Note: See AC and DC Characteristics for values of V

parameters. The V

power supply can be hard-wired to the device or

switchable. When V

is switched, V

PPL

may be ground, no connect with a resistor tied to ground, or less than V

+ 2.0 V. Refer

to Functional Description. Device is either powered-down, erase inhibit or program inhibit.

Bus Operations

Command

Comments

Standby

Wait for V

Ramp to V

PPH

(see Note)

Write

Embedded Program Setup Command

Data = 10h or 50h

Write

Embedded Program Command

Valid Address/Data

Read

Data

Polling to Verify Completion

Read

Available for Read Operations

START

Apply V

PPH

Write Embedded Setup Program Command

Write Embedded

Program Command (A/D)

Programming Completed

Yes

Data# Poll Device

Increment Address

18880C-7

Figure 2.

Embedded Programming Algorithm

Last Address

Am28F512A

Write Operation Status

Data Polling--DQ7

The device features Data# Polling as a method to indi-
cate to the host system that the Embedded algorithms
are either in progress or completed.

While the Embedded Programming algorithm is in oper-
ation, an attempt to read the device at a valid address
will produce the complement of expected Valid data on
DQ7. Upon completion of the Embedded Program algo-
rithm an attempt to read the device at a valid address will
produce Valid data on DQ7. The Data# Polling feature is
valid after the rising edge of the second WE# pulse of
the two write pulse sequence.

While the Embedded Erase algorithm is in operation,
DQ7 will read "0" until the erase operation is com-
pleted. Upon completion of the erase operation, the
data on DQ7 will read "1." The Data# Polling feature is
valid after the rising edge of the second WE# pulse of
the two Write pulse sequence.

The Data# Polling feature is only active during Embed-
ded Programming or erase algorithms.

See Figures 3 and 4 for the Data# Polling timing spec-
ifications and diagrams. Data# Polling is the standard
method to check the write operation status, however,
an alternative method is available using Toggle Bit.

START

Fail

DQ7 = Data

DQ5 = 1

Pass

Yes

Read Byte

(DQ0DQ7)

Addr = VA

Read Byte

(DQ0DQ7)

Addr = VA

Yes

VA = Byte address for programming

= XXXXh during chip erase

18880C-8

Note:
DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5 or after DQ5.

Figure 3.

Data

Polling Algorithm

Am28F512A

Toggle Bit--DQ6

The device also features a "Toggle Bit" as a method to
indicate to the host system that the Embedded algo-
rithms are either in progress or completed.

Successive attempts to read data from the device at a
valid address, while the Embedded Program algorithm
is in progress, or at any address while the Embedded
Erase algorithm is in progress, will result in DQ6 tog-
gling between one and zero. Once the Embedded Pro-
gram or Erase algorithm is completed, DQ6 will stop

toggling to indicate the completion of either Embedded
operation. Only on the next read cycle will valid data be
obtained. The toggle bit is valid after the rising edge of
the first WE# pulse of the two write pulse sequence, un-
like Data# Polling which is valid after the rising edge of
the second WE# pulse. This feature allows the user to
determine if the device is partially through the two write
pulse sequence.

See Figures 5 and 6 for the Toggle Bit timing specifica-
tions and diagrams.

START

Fail

DQ6 = Toggle

DQ5 = 1

Pass

Yes

Read Byte

(DQ0DQ7)

Addr = VA

Read Byte

(DQ0DQ7)

Addr = VA

Yes

DQ6 = Toggle

VA = Byte address for programming

= XXXXh during chip erase

18880C-10

Note:
DQ6 is rechecked even if DQ5 = "1" because DQ6 may stop toggling at the same time as DQ5 changing to "1".

Figure 5.

Toggle Bit Algorithm

Am28F512A

DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has
exceeded the specified limits. This is a failure condi-
tion and the device may not be used again (internal
pulse count exceeded). Under these conditions DQ5
will produce a "1." The program or erase cycle was not
successfully completed. Data# Polling is the only op-
erating function of the device under this condition. The
CE# circuit will partially power down the device under
these conditions (to approximately 2 mA). The OE#
and WE# pins will control the output disable functions
as described in the Command Definitions table in the
corresponding device data sheet.

Parallel Device Erasure

The Embedded Erase algorithm greatly simplifies par-
allel device erasure. Since the erase process is internal
to the device, a single erase command can be given to
multiple devices concurrently. By implementing a paral-
lel erase algorithm, total erase time may be minimized.

Note that the Flash memories may erase at different
rates. If this is the case, when a device is completely
erased, use a masking code to prevent further erasure
(over-erasure). The other devices will continue to erase
until verified. The masking code applied could be the
read command (00h).

Power-Up/Power-Down Sequence

The device powers-up in the Read only mode. Power
supply sequencing is not required. Note that if V

1.0 Volt, the voltage difference between V

and V

should not exceed 10.0 Volts. Also, the device has a
rise V

rise time and fall time specification of 500 ns

minimum.

Reset Command

The Reset command initializes the Flash memory de-
vice to the Read mode. In addition, it also provides the
user with a safe method to abort any device operation
(including program or erase).

The Reset must be written two consecutive times after
the Setup Program command (10h or 50h). This will
reset the device to the Read mode.

Following any other Flash command, write the Reset
command once to the device. This will safely abort any
previous operation and initialize the device to the Read
mode.

The Setup Program command (10h or 50h) is the only
command that requires a two-sequence reset cycle. The
first Reset command is interpreted as program data.
However, FFh data is considered as null data during pro-
gramming operations (memory cells are only pro-
grammed from a logical "1" to "0"). The second Reset
command safely aborts the programming operation and
resets the device to the Read mode.

Memory contents are not altered in any case.

CE#

OEH

WE#

OE#

Data

DQ0DQ7

DQ6 =

DQ6

Stop Toggling

DQ0DQ7

Valid

18880C-11

Note:

*DQ6 stops toggling (The device has completed the Embedded operation.)

Figure 6.

AC Waveforms for Toggle Bit during Embedded Algorithm Operations

Am28F512A

This detailed information is for your reference. It may
prove easier to always issue the Reset command two
consecutive times. This eliminates the need to deter-
mine if you are in the Setup Program state or not.

In-System Programming Considerations

Auto Select Command

AMD's Flash memories are designed for use in appli-
cations where the local CPU alters memory contents.
In order to correctly program any Flash memories

in-system, manufacturer and device codes must be
accessible while the device resides in the target
system. PROM programmers typically access the sig-
nature codes by raising A9 to a high voltage. However,
multiplexing high voltage onto address lines is not a
generally desired system design practice.

The device contains an Auto Select operation to supple-
ment traditional PROM programming methodologies.
The operation is initiated by writing 80h or 90h into the
command register. Following this command, a read
cycle address 0000h retrieves the manufacturer code of
01h (AMD). A read cycle from address 0001h returns
the device code (see the Auto Select Code table of the
corresponding device data sheet). To terminate the op-
eration, it is necessary to write another valid command,
such as Reset (00h or FFh), into the register.

Am28F512A

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . . 65

C to +150

Plastic Packages . . . . . . . . . . . . . . . 65

C to +125

Ambient Temperature
with Power Applied. . . . . . . . . . . . . .55

C to + 125

Voltage with Respect To Ground
All pins except A9 and V

(Note 1) . . . . . . . . . . . . . . . . . . . . . . . 2.0 V to +7.0 V

(Note 1). . . . . . . . . . . . . . . . . . . . 2.0 V to +7.0 V

(Note 2). . . . . . . . . . . . . . . . . . . . 2.0 V to +14.0 V

(Note 2). . . . . . . . . . . . . . . . . . . 2.0 V to +14.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During

voltage transitions, inputs may overshoot V

to 2.0 V

for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is V

+ 0.5 V. During voltage transitions,

input and I/O pins may overshoot to V

+ 2.0 V for

periods up to 20 ns.

2. Minimum DC input voltage on A9 and V

pins is 0.5 V.

During voltage transitions, A9 and V

may overshoot

to 2.0 V for periods of up to 20 ns. Maximum DC

input voltage on A9 and V

is +13.0 V which may

overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output shorted to ground at a time.

Duration of the short circuit should not be greater than
one second.

Stresses above those listed under "Absolute Maximum Rat-
ings" may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for
extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

) . . . . . . . . . . .0

C to +70

Industrial (I) Devices

Ambient Temperature (T

) . . . . . . . . .40

C to +85

Extended (E) Devices

Ambient Temperature (T

) . . . . . . . .55

C to +125

Supply Voltages

. . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V

Voltages

Read . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +12.6 V

Program, Erase, and Verify . . . . . . +11.4 V to +12.6 V

Operating ranges define those limits between which the
functionality of the device is guaranteed.

Am28F512A

DC CHARACTERISTICS over operating range unless otherwise specified

TTL/NMOS Compatible

Notes:
1. Caution: The Am28F512A must not be removed from (or inserted into) a socket when V

or V

is applied. If V

1.0

volt, the voltage difference between V

and V

should not exceed 10.0 volts. Also, the Am28F512A has a V

rise time

and fall time specification of 500 ns minimum.

2. I

CC1

is tested with OE

= V

to simulate open outputs.

3. Maximum active power usage is the sum of I

and I

4. Not 100% tested.

Parameter

Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

Input Leakage Current

= V

Max, V

= V

or V

1.0

µA

Output Leakage Current

= V

Max, V

OUT

= V

or V

1.0

µA

CCS

Standby Current

= V

Max, CE

= V

0.2

1.0

CC1

Active Read Current

CC =

Max, CE

= V

IL,

= V

OUT

= 0 mA, at 6 MHz

CC2

Programming Current

Programming in Progress (Note 4)

CC3

Erase Current

Erasure in Progress (Note 4)

PPS

Standby Current

= V

PPL

1.0

µA

PP1

Read Current

= V

PPH

200

µA

= V

PPL

1.0

PP2

Programming Current

= V

PPH

Programming in Progress (Note 4)

PP3

Erase Current

= V

PPH

Erasure in Progress (Note 4)

Input Low Voltage

0.5

0.8

Input High Voltage

2.0

+ 0.5

Output Low Voltage

= 5.8 mA, V

= V

Min

0.45

OH1

Output High Voltage

= 2.5 mA, V

= V

Min

2.4

A9 Auto Select Voltage

A9 = V

11.5

13.0

A9 Auto Select Current

A9 = V

Max, V

= V

Max

µA

PPL

during Read-Only

Operations

Note: Erase/Program are inhibited
when V

= V

PPL

0.0

+2.0

PPH

during Read/Write

Operations

11.4

12.6

LKO

Low V

Lock-out Voltage

3.2

3.7

Am28F512A

DC CHARACTERISTICS

CMOS Compatible

Notes:
1. Caution: The Am28F512A must not be removed from (or inserted into) a socket when V

or V

is applied. If V

1.0 volt,

the voltage difference between V

and V

should not exceed 10.0 volts. Also, the Am28F512A has a V

rise time and fall

time specification of 500 ns minimum.

2. I

CC1

is tested with OE

= V

to simulate open outputs.

3. Maximum active power usage is the sum of I

and I

4. Not 100% tested.

Parameter

Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

Input Leakage Current

= V

Max, V

= V

or V

1.0

µA

Output Leakage Current

= V

Max, V

OUT

= V

or V

1.0

µA

CCS

Standby Current

= V

Max, CE

= V

+ 0.5 V

100

µA

CC1

Active Read Current

= V

Max, CE

= V

IL,

= V

OUT

= 0 mA, at 6 MHz

CC2

Programming Current

= V

Programming in Progress (Note 4)

CC3

Erase Current

= V

Erasure in Progress (Note 4)

PPS

Standby Current

= V

PPL

1.0

µA

PP1

Read Current

= V

PPH

200

µA

PP2

Programming Current

= V

PPH

Programming in Progress (Note 4)

PP3

Erase Current

= V

PPH

Erasure in Progress (Note 4)

Input Low Voltage

0.5

0.8

Input High Voltage

0.7 V

+ 0.5

Output Low Voltage

= 5.8 mA, V

= V

Min

0.45

OH1

Output High Voltage

= 2.5 mA, V

= V

Min

0.85 V

OH2

= 100 µA, V

= V

Min

0.4

A9 Auto Select Voltage

A9 = V

11.5

13.0

A9 Auto Select Current

A9 = V

Max, V

= V

Max

µA

PPL

during Read-Only

Operations

Note: Erase/Program are inhibited
when V

= V

PPL

0.0

+ 2.0

PPH

during Read/Write

Operations

11.4

12.6

LKO

Low V

Lock-out Voltage

3.2

3.7

Am28F512A

SWITCHING TEST WAVEFORMS

SWITCHING CHARACTERISTICS over operating range unless otherwise specified

AC Characteristics--Read Only Operation

Notes:
1. Guaranteed by design not tested.

2. Not 100% tested.

Parameter Symbols

Parameter Description

Am28F512A Speed Options

Unit

JEDEC

Standard

-70

-90

-120

-150

-200

AVAV

Read Cycle Time (Note 2)

Min

120

150

200

ELQV

Chip Enable Access Time

Max

120

150

200

AVQV

ACC

Address Access Time

Max

120

150

200

GLQV

Output Enable Access Time

Max

ELQX

Chip Enable to Output in Low Z
(Note 2)

Min

EHQZ

Chip Disable to Output in High Z
(Note 1)

Max

GLQX

OLZ

Output Enable to Output in Low Z
(Note 2)

Min

GHQZ

Output Disable to Output in
High Z (Note 2)

Max

AXQX

Output Hold from first of Address,
CE

, or OE

Change (Note 2)

Min

VCS

Setup Time to Valid Read

(Note 2)

Min

µs

18880C-17

3 V

0 V

Input

Output

1.5 V

Test Points

AC Testing for -70 devices: Inputs are driven at 3.0 V for a
logic "1" and 0 V for a logic "0". Input pulse rise and fall times
are

10 ns.

2.4 V

0.45 V

Input

Output

Test Points

2.0 V

0.8 V

AC Testing (all speed options except -70): Inputs are driven
at 2.4 V for a logic "1" and 0.45 V for a logic "0". Input pulse
rise and fall times are

10 ns.

Am28F512A

AC Characteristics--Write/Erase/Program Operations

Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC

Characteristics for Read Only operations.

2. Embedded Program Operation of 14 µs consists of 10 µs program pulse and 4 ms write recovery before read. This is the

minimum time for one pass through the programming algorithm.

3. Embedded Erase Operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a

typical time for one embedded erase operation.

4. Not 100% tested.

Parameter Symbols

Parameter Description

Am28F512A Speed Options

Unit

JEDEC

Standard

-70

-90

-120

-150

-200

AVAV

Write Cycle Time (Note 4)

Min

120

150

200

AVWL

Address Setup Time

Min

WLAX

Address Hold Time

Min

DVWH

Data Setup Time

Min

WHDX

Data Hold Time

Min

OEH

Output Enable Hold Time
for Embedded Algorithm only

Min

µs

GHWL

Read Recovery Time before Write

Min

µs

ELWLE

CSE

Chip Enable Embedded Algorithm
Setup Time

Min

WHEH

Chip Enable Hold Time

Min

WLWH

Write Pulse Width

Min

WHWL

WPH

Write Pulse Width HIGH

Min

WHWH3

Embedded Programming Operation
(Note 2)

Min

µs

WHWH4

Embedded Erase Operation (Note 2)

Typ

VPEL

Setup Time to Chip Enable LOW

(Note 4)

Min

100

VCS

Setup Time to Chip Enable LOW

(Note 4)

Min

µs

VPPR

Rise Time 90% V

PPH

(Note 4)

Min

500

VPPF

Fall Time 10% V

PPL

(Note 4)

Min

500

LKO

< V

LKO

to Reset (Note 4)

Min

100

Am28F512A

AC CHARACTERISTICS--WRITE/ERASE/PROGRAM OPERATIONS

Alternate CE

Controlled Writes

Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC

Characteristics for Read Only operations.

2. Embedded Program Operation of 14 µs consists of 10 µs program pulse and 4 ms write recovery before read. This is the

minimum time for one pass through the programming algorithm.

3. Embedded Erase Operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a

typical time for one embedded erase operation.

4. Not 100% tested.

Parameter Symbols

Parameter Description

Am28F512A Speed Options

Unit

JEDEC

Standard

-70

-90

-120

-150

-200

AVAV

Write Cycle Time (Note 4)

Min

120

150

200

AVEL

Address Setup Time

Min

ELAX

Address Hold Time

Min

DVEH

Data Setup Time

Min

EHDX

Data Hold Time

Min

OEH

Output Enable Hold Time
for Embedded Algorithm only

Min

µs

GHEL

Read Recovery Time before Write

Min

WLEL

WE# Setup Time by CE

Min

EHWK

WE# Hold Time

Min

ELEH

Write Pulse Width

Min

EHEL

CPH

Write Pulse Width HIGH

Min

EHEH3

Embedded Programming Operation
(Note 2)

Min

µs

EHEH4

Embedded Erase Operation (Note 3)

Typ

sec

VPEL

Setup Time to Chip Enable LOW

(Note 4)

Min

100

VCS

Setup Time to Chip Enable LOW

(Note 4)

Min

µs

VPPR

Rise Time 90% V

PPH

(Note 4)

Min

500

VPPF

Fall Time 10% V

PPL

(Note 4)

Min

500

LKO

< V

LKO

to Reset (Note 4)

Min

100

Am28F512A

ERASE AND PROGRAMMING PERFORMANCE

Notes:
1. 25

C, 12 V V

2. Maximum time specified is lower than worst case. Worst case is derived from the Embedded Algorithm internal counter which

allows for a maximum 6000 pulses for both program and erase operations. Typical worst case for program and erase is
significantly less than the actual device limit.

3. Typical worst case = 84 µs. DQ5 = "1" only after a byte takes longer than 96 ms to program.

LATCHUP CHARACTERISTICS

PIN CAPACITANCE

Note: Sampled, not 100% tested. Test conditions T

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Limits

Comments

Min

Typ

(Note 1)

Max

(Note 2)

Unit

Chip Erase Time

sec

Excludes 00h programming prior to erasure

Chip Programming Time

sec

Excludes system-level overhead

Write/Erase Cycles

100,000

Cycles

Byte Programming Time

µs

(Note 3)

Parameter

Min

Max

Input Voltage with respect to V

on all pins except I/O pins (Including A9 and V

)

1.0 V

13.5 V

Input Voltage with respect to V

on all pins I/O pins

1.0 V

+ 1.0 V

Current

100 mA

+100 mA

Includes all pins except V

. Test conditions: V

= 5.0 V, one pin at a time.

Parameter

Symbol

Parameter Description

Test Conditions

Typ

Max

Unit

Input Capacitance

= 0

OUT

Output Capacitance

OUT

= 0

IN2

Input Capacitance

= 0

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

Years

125

Years

Am28F512A

PHYSICAL DIMENSIONS

TSR032--32-Pin Reversed Thin Small Outline Package (measured in millimeters)

DATA SHEET REVISION SUMMARY FOR AM28F512A

Revision C

Deleted -75, -95, and -250 speed options. Matched for-
matting to other current data sheets.

Revision C+1

Programming In A PROM Programmer

Deleted the paragraph "(Refer to the AUTO SELECT
paragraph in the ERASE, PROGRAM, and READ
MODE section for programming the Flash memory de-
vice in-system)."

Revision C+2

Product Selector Guide

Corrected maximum access time for -200 to 200 ns.

Connection Diagrams

On standard TSOP, corrected pin 9 to V

and pin 10

to NC. On reverse TSOP, corrected pin 23 to NC and
pin 24 to V

Trademarks

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

18.30
18.50

19.80
20.20

7.90
8.10

0.50 BSC

0.05
0.15

0.95
1.05

16-038-TSOP-2
TSR032
DA95
3-25-97 lv

Pin 1 I.D.

1.20

MAX

0.50
0.70

0.10
0.21

0.08
0.20

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AM28F512A-90EIB

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AM28F512A-90EIB