A D V A N C E D M I C R O D E V I C E S
Am8530H/Am85C30
Serial Communications Controller
1992 Technical Manual
ii
1992 Advanced Micro Devices, Inc.
Advanced Micro Devices reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
This publication neither states nor implies any warranty of any kind, including but not limited to implied warrants of merchan-
tability or fitness for a particular application. AMD assumes no responsibility for the use of any circuitry other than the circuitry
in an AMD product.
The information in this publication is believed to be accurate in all respects at the time of publication, but is subject to change
without notice. AMD assumes no responsibility for any errors or omissions, and disclaims responsibility for any consequences
resulting from the use of the information included herein. Additionally, AMD assumes no responsibility for the functioning of
undescribed features or parameters.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Trademarks
Z80 and ZBus are registered trademarks of Zilog, Inc.
Z8000, Z8030, and Z8530 are trademarks of Zilog, Inc.
MULTIBUS is a registered trademark of Intel Corporation
PAL is a registered trademark of Advanced Micro Devices, Inc.
PREFACE
Thank you for your interest in the SCC, one of the most popular Serial Data ICs available
today. This manual is intended to provide answers to technical questions about the
Am8530H and Am85C30.
If you have already used the Am8530H and are familiar with the previous editions of this
Technical Manual, you will find that some chapters are virtually unchanged. The
Am8030's functionality, however, has been omitted from this revision since a CMOS
Am8030 was not developed. You can, however, consult the previous Am8030/8530 Tech-
nical Manual revision for information pertaining to Am8030 operation.
Functional descriptions of enhancements added to the Am85C30 have been included in
this Technical Manual revision. These enhancements improve the Am85C30's functional-
ity and allow it to be used more effectively in high-speed applications. These enhance-
ments include:
s
a 10 x 19-bit SDLC/HDLC frame status FIFO array
s
a 14-bit SDLC/HDLC frame byte counter
s
automatic SDLC/HDLC opening flag transmission
s
automatic SDLC/HDLC Tx Underrun/EOM flag resetting
s
automatic SDLC/HDLC Tx CRC generator presetting
s
RTS
pin synchronization to closing SDLC/HDLC flag
s
DTR
/
REQ
deactivation delay significantly reduced
s
external PCLK to RxC or TxC synchronization requirement eliminated for PCLK divide-
by-four operation
s
complete SDLC/HDLC CRC character reception
s
reduced
INT
response time
s
Write data setup time to rising edge of
WR
requirement eliminated
s
Write Registers WR3, WR4, WR5, and WR10 made readable
Most users read only chapters that are of interest to them. If you are designing the micro-
computer hardware using the SCC as a peripheral, you will want to read the Applications
Section in Chapter 7. Application notes covering the interfacing of the Am8530H (pre H-
step and CMOS versions only) to the 8086/80186, 68000 processors and Am7960 Data
Coded Transceiver have been included.
As was the case with the NMOS SCC, some points to look out for when using the
Am85C30 are:
s
Follow the worksheet for initialization (Chapter 7). Unexplainable operations may occur if
this procedure is not followed.
s
Watch out for the Write Recovery time violation. The specification for this (Trc) was
changed on both the H-step and CMOS version. It is now referenced from falling edge to
falling edge of the Read/Write pulse. Trc is spec'd at 4 PCLKs for the NMOS H-step and 3
PCLKs (best case)/3.5 PCLKs for the Am85C30.
s
Ensure Mode bits are not changed when writing commands. Each Mode bit affects only
one function and a Command bit entry requires a rewrite of the entire register; therefore,
care must be taken to insure the integrity of the Mode bits whenever a new command is
issued.
s
Any unused input pins should be tied high.
TABLE OF CONTENTS
Chapter 1
General Information
1.1 Introduction
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Capabilities
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Block
Diagram
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Pin
Functions
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Pin
Descriptions
18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1
System Interface Pin Descriptions
18
. . . . . . . . . . . . . . .
1.5.2
Serial Channel Pin Descriptions
19
. . . . . . . . . . . . . . . .
Chapter 2
System Interface
2.1
Introduction
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Registers
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
System Timings
25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Read Cycle
25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2
Write Cycle
25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3
Interrupt Acknowledge Cycle
25
. . . . . . . . . . . . . . . . . . .
2.4
Register Access
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Am85C30 Enhancement Register Access
27
. . . . . . . . . . . . . .
2.6
Reset
212
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3
I/O Programming Functional Description
3.1
Introduction 33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Polling
33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Interrupt Sources
33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Interrupt Control
34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1
Interrupt Enable Bit
34
. . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2
Interrupt Pending Bit
35
. . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3
Interrupt Under Service Bit
35
. . . . . . . . . . . . . . . . . . . .
3.4.4
Disable Lower Chain Bit
35
. . . . . . . . . . . . . . . . . . . . . .
3.5
Interrupt Operations
36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
Multiple Interrupt Priority Resolution
36
. . . . . . . . . . . . .
3.5.2
Interrupt Without Acknowledge
38
. . . . . . . . . . . . . . . . .
3.5.3
Interrupt With Acknowledge With Vector
38
. . . . . . . . . .
3.5.4
Interrupt With Acknowledge Without Vector
310
. . . . . . .
3.5.5
Lower Priority Interrupt Masking
310
. . . . . . . . . . . . . . . .
3.6
Receive Interrupts
310
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
Receive Interrupts Disabled
310
. . . . . . . . . . . . . . . . . . . .
3.6.2
Receive Interrupt on First Character or
Special Condition
310
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3
Receive Interrupt on All Receive Characters or
Special Conditions
311
. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.4
Receive Interrupt on Special Conditions
311
. . . . . . . . . .
3.7
Transmit Interrupts
312
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
External/Status Interrupts
313
. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1
Sync/Hunt
313
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2
Break/Abort
314
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.3
Zero Count
314
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.4
Tx Underrun/EOM
315
. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.5
Clear To Send
315
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.6
Data Carrier Detect
315
. . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents
AMD
3.9
Block Transfers
315
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.1
Wait on Transmit
316
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2
Wait on Receive
316
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.3
DMA Requests
317
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.3.1 DMA Request on Transmit
(using
W
/
REQ
)
317
. . . . . . . . . . . . . . . . . . . . . .
3.9.3.2 DMA Request on Transmit
(using
DTR
/
REQ
)
318
. . . . . . . . . . . . . . . . . . . .
3.9.3.3
DTR
/
REQ
Deactivation Timing
319
. . . . . . . . . .
3.9.3.4 DMA Request on Receive (using
W
/
REQ
)
320
.
Chapter 4
Data Communication Modes Functional Description
4.1
Introduction
43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Protocols
43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1
Asynchronous
43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2
Synchronous Transmission
44
. . . . . . . . . . . . . . . . . . . .
4.2.2.1 Synchronous Character-Oriented
Protocol
44
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2.2 Synchronous Bit-Oriented
44
. . . . . . . . . . . . . .
4.3
Mode Selection
45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Receiver Overview
46
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1
Rx Character Length
47
. . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2
Rx Parity
48
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3
Rx Modem Control
49
. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Transmitter Overview
49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1
Tx Character Length
49
. . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2
Tx Parity
411
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.3
Break Generation
411
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.4
Transmit Modem Control
411
. . . . . . . . . . . . . . . . . . . . . .
4.5.5
Auto
RTS
Reset
411
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
Asynchronous Mode Operation
412
. . . . . . . . . . . . . . . . . . . . . . .
4.6.1
Receiver Operation
412
. . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1.1 Receiver Initialization
412
. . . . . . . . . . . . . . . . .
4.6.1.2 Framing Error
412
. . . . . . . . . . . . . . . . . . . . . . .
4.6.1.3 Break Detection
413
. . . . . . . . . . . . . . . . . . . . . .
4.6.1.4 Clock Selection
413
. . . . . . . . . . . . . . . . . . . . . .
4.6.2
Transmitter Operation
413
. . . . . . . . . . . . . . . . . . . . . . . .
4.6.2.1 Transmitter Initialization
413
. . . . . . . . . . . . . . .
4.6.2.2 Stop Bit Selection
413
. . . . . . . . . . . . . . . . . . . .
4.7
SDLC Mode Operation
414
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1
Receiver Operation
414
. . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1.1 Flag Detect Output
414
. . . . . . . . . . . . . . . . . . .
4.7.1.2 Receiver Initialization
414
. . . . . . . . . . . . . . . . .
4.7.1.3 10x19-Bit Frame Status FIFO
414
. . . . . . . . . . .
4.7.1.3.1 FIFO Enabling/Disabling
415
. . . . . . . .
4.7.1.3.2 FIFO Read Operation
415
. . . . . . . . . .
4.7.1.3.3 FIFO Write Operation
415
. . . . . . . . . .
4.7.1.3.4 14-Bit Byte Counter
415
. . . . . . . . . . .
4.7.1.3.5 Am85C30 Frame Status
FIFO Operation Clarification
418
. . . . .
4.7.1.3.6 Am85C30 Aborted Frame
Handling When Using the 10x19
Frame Status FIFO
419
. . . . . . . . . . . .
4.7.1.4 Address Search Mode
419
. . . . . . . . . . . . . . . . .
4.7.1.5 Abort Detection
420
. . . . . . . . . . . . . . . . . . . . . .
4.7.1.6 Residue Bits
421
. . . . . . . . . . . . . . . . . . . . . . . .
4.7.2
SDLC Mode CRC Polynomial Selection
421
. . . . . . . . . .
4.7.2.1 Rx CRC Initialization
422
. . . . . . . . . . . . . . . . . .
4.7.2.2 Rx CRC Enabling
422
. . . . . . . . . . . . . . . . . . . .
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